US 8,799,553 B2Granted

Memory controller mapping on-the-fly

AssigneeApple Inc.

InventorsIan Hendry, Rajabali Koduri, Jeffry Gonion

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Abstract

Systems, methods, and devices for dynamically mapping and remapping memory when a portion of memory is activated or deactivated are provided. In accordance with an embodiment, an electronic device may include several memory banks, one or more processors, and a memory controller. The memory banks may store data in hardware memory locations and may be independently deactivated. The processors may request the data using physical memory addresses, and the memory controller may translate the physical addresses to hardware memory locations. The memory controller may use a first memory mapping function when a first number of memory banks is active and a second memory mapping function when a second number is active. When one of the memory banks is to be deactivated, the memory controller may copy data from only the memory bank that is to be deactivated to the active remainder of memory banks.

Claims8

Dependent claims

An electronic device, comprising:

a plurality of memory banks having hardware memory locations, wherein at least one of the plurality of memory banks is configured to be selectively deactivated;
one or more processors capable of issuing memory requests via physical memory addresses;
and
a memory controller configured to dynamically map the physical memory addresses to the hardware memory locations using a first mapping equation when three memory banks are active and a second mapping equation when two memory banks are active, wherein the first mapping equation comprises the following relationships:
BankIndex=Floor(PAddr/TotalBanks) and DIMMAddr=MOD(PAddr*BankSize, TotalMemory)+BankIndex, where PAddr represents a physical memory address, DIMMAddr represents the hardware memory location to which the physical memory address is mapped when three memory banks of the plurality of memory banks are active, BankSize represents a quantity of physical memory addresses of each of the plurality of memory banks, TotalBanks represents a total number of active memory banks of the plurality of memory banks, and TotalMemory represents a total number of hardware memory locations among the active memory banks of the plurality of memory banks;
wherein the second mapping equation comprises the following relationships:
ALT_DIMMAddr3_2 = If(DIMMAddr < ReducedMemory3_2,
Then DIMMAddr,
Else If(BankReindex3_2 < FirstBankEntries3_2,
,
Then FirstBankOffset3_2 + BankReindex3_2,
Else SecondBankOffset3_2 + BankReindex3_2))
where:
BankReindex3_2 = If(DIMMAddr < ReducedMemory3_2,
Then −1,
;
Else DIMMAddr − ReducedMemory3_2)
FirstBankEntries3_2 = Floor(BankSize / TotalBanks) ;
FirstBankOffset3_2 =
;
and
Floor(ReducedBanks3_2 * BankSize / TotalBanks)
SecondBankOffset3_2 = FirstBankEntries3_2 + BankSize
−Floor(BankSize / TotalBanks) + 3
,
where ALT DIMMAddr3—2 represents a storage cell to which a physical address is mapped when two memory banks are active, ReducedMemory3—2 represents a quantity of hardware memory locations available across the active two memory banks, and ReducedBanks3—2 represents a number of the active two memory banks.

23 more elements

An electronic device, comprising:

a plurality of memory banks having hardware memory locations, wherein at least one of the plurality of memory banks is configured to be selectively deactivated;
one or more processors capable of issuing memory requests via physical memory addresses;
and
a memory controller configured to dynamically map the physical memory addresses to the hardware memory locations using a first mapping equation when three memory banks are active and a second mapping equation when two memory banks are active, wherein the first mapping equation comprises the following relationships:
BankIndex=Floor(PAddr/TotalBanks) and DIMMAddr=MOD(PAddr*BankSize, TotalMemory)+BankIndex, where PAddr represents a physical memory address, DIMMAddr represents the hardware memory location to which the physical memory address is mapped when three memory banks of the plurality of memory banks are active, BankSize represents a quantity of physical memory addresses of each of the plurality of memory banks, TotalBanks represents a total number of active memory banks of the plurality of memory banks, and TotalMemory represents a total number of hardware memory locations among the active memory banks of the plurality of memory banks;
wherein the memory controller is configured to dynamically map the physical memory addresses to hardware memory locations using a third mapping equation when one memory bank is active, wherein the third mapping equation comprises the following relationships:
ALT_DIMMAddr2_1 = If(ALT_DIMMAddr3_2 < ReducedMemory2_1,
Then ALT_DIMMAddr3_2,
Else If(BankReindex2_1 < FirstBankEntries2_1,
,
Then FirstBankOffset2_1 + Bank_Reindex2_1,
Else BankReindex2_1))
where:
BankReindex2_1 = If(ALT_DIMMAddr3_2 < ReducedMemory2_1,
Then −1,
;
Else ALT_DIMMAddr3_2 − ReducedMemory2_1)
FirstBankEntries2_1 = Floor(BankSize / TotalBanks) + 1
;
and
FirstBankOffset2_1 = Floor(ReducedBanks2_1 * BankSize / TotalBanks) + 1 ,
where ALT_DIMMAddr2—1 represents the hardware memory location to which a physical address is mapped when one memory bank is active, ReducedMemory2—1 represents a quantity of hardware memory locations available across the one active memory bank, and ReducedBanks2—1 represents the number of the one active memory bank.

19 more elements

Dependencies are inferred from the claim text.

Facts

Application: 12/895,689Filed 30 Sep 2010 · us provisional application
Priority: 13 Apr 2010
Published: US 2011/0252180 A113 Oct 2011
Granted: 5 Aug 2014
Term ends: Not estimatedThe source records don’t support an estimate.

Classification17 codes

G06F 3/0647
Horizontal data movement in storage systems, i.e. moving data in between storage devices or systems: migration mechanisms
G06F 1/3203
Means for saving power: power management, i.e. event-based initiation of a power-saving mode
G06F 1/3225
Monitoring of peripheral devices: of memory devices
G06F 1/3275
Power saving in peripheral device: power saving in memory, e.g. RAM, cache