Microcontroller with special banking instructions

#The present disclosure relates to integrated microcontrollers, and, more particularly to memory access of the microcontroller.

#Linearly accessible data memory space requires that a large number of memory bytes, for example, random access memory (RAM) bytes, be placed contiguously and addressable in an address space. The linear memory can then be fully addressed through an address whose length depends on the size of the RAM. Microcontrollers having long instructions such as 32-bit microcontrollers or microcontrollers with multiple instruction words can easily embed such a long address within the op-code of an instruction. However, smaller architectures, for example, 8-bit architectures with efficient limited instruction length often use an instruction size of for example 10-15 bits that does not allow for storing long addresses. Even though multiple word instructions could accommodate longer addresses, this counters compact coding and therefore, such processor architectures may not be able to address a large linear address space directly. Hence, memory banking is an efficient means to provide full access to a larger memory. In memory banking, only a limited amount, i.e. a single memory bank, is made available by means of a pointer. An instruction can then contain enough bits to access all memory locations within the selected memory bank. To switch to memory locations outside a selected bank, the pointer needs to be modified.

#For example, many RISC architecture microcontrollers can only access a limited amount of bytes, for example, 32 or 64 bytes of memory directly through their instructions. By using multiple banks of 32 or 64 bytes, additional memory may be accessed. Microcontrollers are generally a combination of a microprocessor or central processing unit (CPU) with peripherals and memory on a single chip. Thus, microcontrollers which use the memory banking concept further face the problem that many special function registers used, for example, for control of these peripherals and internal functions, need to be accessed by the instruction set. Thus, these special function registers are made available by mapping them into the data memory. Because access to some special function registers is critical while executing a program, in many microcontrollers some of these special function registers need to be available all the time. For example, if special function registers are only accessible through the memory, the special function register used for selecting a memory bank needs to be accessible all the time or otherwise, a user would be stuck in a memory bank that does not make this register available. To accommodate this, in many microcontrollers, data memory mapping places a minimum number of such Special Function Registers (SFR) in each bank of the memory. However, this renders the data memory non-contiguous because the non-mapped memory blocks are separated by the memory-mapped registers.

#FIG. 1 shows a block diagram of a conventional microcontroller;

#FIG. 2 shows a block diagram of an exemplary microcontroller according to an embodiment;

#FIG. 3 is a block diagram showing a conventional banked memory;

#According to the teachings of this disclosure, a non-memory mapped bank select register (BSR) is provided for selecting one of a plurality of memory banks used for direct addressing. A memory mapped register is used for indirect addressing independent from the selected memory bank. The addition of a specialized banking instruction, for example, “Move Literal to BSR Register (MOVLB)” allows all of the data bytes in a bank of memory to be used for general purpose data and therefore allows contiguous addressing across a plurality of the memory banks that do not contain any mapped special function registers. Hence, the BSR register that selects the active memory bank is not mapped in the data register, but may be accessible with a specialized command.

#Thus, a plurality of memory banks are available that do not have or require special registers therein. This allows adjacent banks of the memory to be indirectly addressed via an indirect addressing register (FSR) without concern or need for special function registers (SFR) in each memory bank. This allows addressing of larger blocks of memory, for example, for use as buffers, tables, scratch pad areas, etc. Any functions using a data structure larger than the banked memory size may be thus implemented.

#FIG. 1, shows a simplified block diagram of conventional microcontroller with a data memory that can be accessed with a banking mechanism. A program memory 110 stores a plurality of instructions forming an executable program. Program counter 115 may be designed to have for example 11 bits for addressing a 2 k linear program memory. A stack 120 may be provided to store program counter values when subroutines are executed. The shown exemplary microcontroller is an 8-bit Harvard-type microcontroller that operates with 12-bit instruction words stored in program memory 110. Thus, a central 8-bit data bus 105 may be used to couple various functional elements within the microcontroller, such as for example timer unit 0 and external port B 130. The data memory 125 is coupled with this bus 105 and receives for example an 8-bit address from address multiplexer 140. For direct addressing, address multiplexer 140 combines an address from address data supplied by the instruction register 135 and address data supplied by special function register 145. In direct addressing mode, the instruction register 135, thus, supplies the lower 5 bits and the special function register 145 the upper 3 bits. Thus, according to an embodiment, special function register 145 operates as a bank select register capable of selecting one of 8 different memory banks. In indirect addressing, special function register 145 provides for a complete address with all bits 0-7. Indirect addressing is implemented by accessing special function register INDF which is a virtual register and therefore not a physical register. Any read or write access to this register INDF forces that an indirect access is applied to the data memory 125 via special function register 145, thus, instead of reading or writing register INDF, an indirect data memory access is performed.