System and method for increased efficiency PCI express transaction
AssigneesAdvanced Micro Devices, Inc., ATI Technologies ULC
InventorsBetty Luk, Gordon F. Caruk
Life of this patent
Estimating the term…
Abstract
A system and method using new PCI Express transaction layer packet headers so that unchanged header information within a burst of transactions does not need to be re-transmitted. After the first full packet header of a burst is sent, subsequent packet headers in the burst are smaller. Thus, more reduced headers can be transmitted over time with a resulting increased efficiency. Both sides of the PCI Express transaction must support this system and method for this approach to be enabled. Once enabled, both the PCI Express transmitter and receiver can use the regular full header PCI Express packets as well as the reduced header packets.
Claims28
A method for transmitting a packet stream from a source to a destination, comprising:
- forming a first packet having a first packet type and a first header field;
- and
- forming a second packet having a second packet type, wherein the second packet type is a reduced header type associated with the first packet type, and a second header field is not included in the second packet when the second header field is of the same type as and of equal value to the first header field,
- wherein the second packet includes in its reduced header one of:
- a 16-bit address field associated with a memory read transaction, a 14-bit address field together with a 2-bit indication of power-of-2 byte memory alignment, a 24-bit address field associated with a memory write transaction, or a 22-bit address field together with a 2-bit indication of power-of-2 byte memory alignment.
A method for receiving a packet stream at a destination from a source, comprising:
- receiving from the packet stream a first packet of a first packet type, wherein the first data packet comprises a first header field;
- receiving from the packet stream a second packet having a second packet type, wherein the second packet type is a reduced packet header type associated with the first packet type;
- and
- using the second packet, wherein the using includes deeming the second packet includes a second header field of the same type as and of equal value to the first header field,
- wherein the second packet includes in its reduced header one of:
- a 16-bit address field associated with a memory read transaction, a 14-bit address field together with a 2-bit indication of power-of-2 byte memory alignment, a 24-bit address field associated with a memory write transaction, or a 22-bit address field together with a 2-bit indication of power-of-2 byte memory alignment.
A method for establishing a packet transmission link from a source to a destination, comprising:
- verifying that a destination device supports a reduced header capability;
- wherein the second packet includes in its reduced header one of:
- a 16-bit address field associated with a memory read transaction, a 14-bit address field together with a 2-bit indication of power-of-2 byte memory alignment, a 24-bit address field associated with a memory write transaction, or a 22-bit address field together with a 2-bit indication of power-of-2 byte memory alignment and
- verifying that a source device and the destination device support compatible reduced header capabilities.
A method for transmitting a packet stream from a source to a destination, comprising:
- forming a first packet having a first packet type and a first header field;
- and
- forming a second packet having a second packet type, wherein the second packet type is a compressed packet type that omits data that is redundant with the first packet,
- wherein the first packet and second packet conform to a component interconnect format for use in a computing platform,
- wherein the second packet includes in its reduced header one of:
- a 16-bit address field associated with a memory read transaction, a 14-bit address field together with a 2-bit indication of power-of-2 byte memory alignment, a 24-bit address field associated with a memory write transaction, or a 22-bit address field together with a 2-bit indication of power-of-2 byte memory alignment.
Dependencies are inferred from the claim text.