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US 8,799,545 B2Granted
Restoring stability to an unstable bus
AssigneeHewlett-Packard Development Company, L.P.
InventorsMike Erickson, David Maciorowski
Life of this patent
Estimating the term…
Abstract
A method for restoring stability to an unstable bus includes cycling a clock of the bus a number of times, transmitting a stop bit, cycling a clock line of the bus at least one time and transmitting a stop bit immediately after an acknowledgment bit has been received by a bus master.
Claims11
A method for restoring stability to an unstable inter-integrated circuit (I2C) bus, comprising:
- detecting that a communication error has occurred on the inter-integrated circuit (I2C) bus without knowledge as to whether communication between a bus master and a slave device across the bus is in a read mode or a write mode;
- placing the bus master in a repair mode in response to the detecting of the communication error, while in the repair mode:
- stabilizing the slave device should the slave device be operating in a read mode by:
- cycling a clock line of the inter-integrated circuit (I2C) bus a number of times;
- and
- transmitting a stop bit;
- stabilizing the slave device should the slave device be operating in a write mode by:
- cycling a clock line of the bus at least one time and up to the number of times until an acknowledgment bit has been received by the bus master;
- and
- transmitting a stop bit immediately after the acknowledgment bit has been received by the bus master;
- and
- returning the bus to a normal operating state after transmission of the stop bit immediately after the acknowledgment has been received by the bus master.
9 more elements
A method for restoring stability to an unstable inter-integrated circuit (I2C) bus, comprising:
- detecting that a communication error has occurred on the I2C bus without knowledge as to whether communication between a bus master and a slave device across the bus is in a read mode or a write mode;
- placing the bus master in a repair mode in response to the detecting of the communication error, while in the repair mode:
- stabilizing the slave device should the slave device be operating in a read mode by:
- cycling a clock line of the I2C b s a number of times;
- and
- transmitting a stop bit;
- stabilizing the slave device should the slave device be operating in a write mode by:
- cycling a clock line of the bus at least one time and up to the number of times until an acknowledgment bit has been received by the bus master;
- and
- transmitting a stop bit immediately after the acknowledgment bit has been received by the bus master, wherein the cycling a clock line of a bus is repeated at least a second time in the event that the acknowledgment has not yet been received by the bus master and wherein cycling a clock line of a bus is repeated up to a maximum of nine times in the event that the acknowledgment has not been received by the bus master;
- and
- returning the bus to a normal n state after transmission of the stop bit immediately after the acknowledgment has been received by the bus master.
9 more elements
A method for restoring stability to an unstable inter-integrated circuit (I2C) bus, comprising:
- detecting that a communication error has occurred on the inter-integrated circuit (I2C) bus without knowledge as to whether communication between a bus master and a slave device across the bus is in a read mode or a write mode;
- placing the bus master in a repair mode in response to the detecting of the communication error, while in the repair mode:
- stabilizing the slave device should the slave device be operating in a read mode by:
- cycling a dock line of the inter-integrated circuit (I2C) bus a number of times, the number of times being based upon a number of bits in a data word plus an acknowledgment bit;
- and
- transmitting a stop bit;
- stabilizing the slave device should the slave device be operating in a write mode by:
- cycling a dock line of the bus at least one time and up to the number of times until an acknowledgment bit has been received by the bus master;
- and
- transmitting a stop bit immediately after the acknowledgment bit has been received by the bus master;
- and
- returning the bus to a normal operating state after transmission of the stop bit immediately after the acknowledgment has been received by the bus master.
9 more elements
Dependencies are inferred from the claim text.