Chipset agnostic apparatus and method for serial communication bus port disablement
AssigneeDell Products L.P.
InventorsTimothy Michael Lambert, Sean Hart
Life of this patent
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Abstract
An information handling system (IHS) includes a host computer with a downstream facing host computer serial communication bus port and a serial communication bus host controller, wherein the controller is configured to detect a serial communication bus device connected to the downstream facing host computer serial communication bus port, wherein the serial communication bus device has a pull-up resistor. The IHS further includes a circuit disposed between the serial communication bus host controller and the downstream facing host computer serial communication bus port, the circuit configured to disable the downstream facing host computer serial communication bus port and comprising at least one tri-state buffer.
Claims20
An information handling system (IHS) comprising:
- a host computer comprising a downstream facing host computer serial communication bus port and a serial communication bus host controller in communication with the downstream facing host computer serial communication bus port;
- the serial communication bus host controller in communication with the downstream facing host computer serial communication bus port via a serial communication bus+ data line and a serial communication bus− data line;
- a first tri-state buffer connected to the serial communication bus+ data line;
- a second tri-state buffer connected to the serial communication bus− data line;
- and
- a circuit disposed between the serial communication bus host controller and the downstream facing host computer serial communication bus port, the circuit operable to disable the downstream facing host computer serial communication bus port from detecting presence of a peripheral device directly coupled to the serial communication bus port.
An information handling system (IHS) comprising:
- a host computer comprising a downstream facing host computer serial communication bus port residing within the host computer, and a serial communication bus host controller, wherein the controller is configured to detect a serial communication bus device connected to the downstream facing host computer serial communication bus port, wherein the serial communication bus device has a pull-up resistor;
- and
- a circuit disposed between the serial communication bus host controller and the downstream facing host computer serial communication bus port, the circuit configured to disable the downstream facing host computer serial communication bus port from detecting presence of a peripheral device directly coupled to the serial communication bus port, and wherein the circuit comprises at least one tri-state buffer.
A method of disabling a downstream facing serial communication bus port residing within a host computer, the method comprising:
- providing a circuit disposed between a serial communication bus host controller and the downstream facing serial communication bus port, the circuit comprising a first tri-state buffer and a second tri-state buffer;
- enabling the first tri-state buffer to sink current on a serial communication bus+ line wherein the serial communication bus + line is positioned between a serial communication bus host controller and a downstream facing serial communication bus port;
- enabling the second tri-state buffer to sink current on a serial communication Bus− line wherein the serial communication bus− line is positioned between a serial communication bus host controller and a downstream facing serial communication bus port;
- and thereby
- disabling the downstream facing serial communication bus port from detecting presence of a peripheral device directly coupled to the serial communication bus port.
Dependencies are inferred from the claim text.