Method and system for processing image data on a per tile basis in an image sensor pipeline

A system for processing images, the system comprising:

• one or more circuits in a chip, said one or more circuits comprising an image sensor pipeline (ISP), said ISP comprising one or more control logic circuits and one or more image processing modules that are communicatively coupled to said one or more control logic circuits, wherein said ISP, said one or more control logic circuits, and said one or more image processing modules are integrated on a singe substrate of said chip, and said one or more circuits are operable to:
• communicate, to said one or more processing modules via said one or more control logic circuits, corresponding configuration parameters that are associated with each one of a plurality of data tiles comprising an image as each data tile progresses through the image sensor pipeline;
• and
• process said each one of said plurality of data tiles by said one or more image processing modules utilizing said corresponding configuration parameters in respective processing steps for said each one of said plurality of data tiles, wherein said one or more image processing modules are operable concurrently, and wherein each of said one or more image processing module performs a different image processing function.

A method for processing images, the method comprising:

• in a chip comprising an image sensor pipeline (ISP), said ISP comprising one or more control logic circuits and a plurality of processing modules that are communicatively coupled to said one or more control logic circuits, wherein said ISP, said one or more control logic circuits, and said plurality of processing modules are integrated on a single substrate of said chip:
• communicating, to said plurality of processing modules via said one or more control logic circuits, corresponding configuration parameters that are associated with each one of a plurality of data tiles comprising an image as each data tile progresses through said ISP;
• and
• processing said each one of said plurality of data tiles utilizing said corresponding configuration parameters, wherein said processing comprises concurrently processing a data tile of said plurality of data tiles by said plurality of processing modules, wherein each of said plurality of processing modules performs separate processing steps.

A method for processing images, the method comprising:

• in a chip comprising an image sensor pipeline (ISP), said ISP comprising one or more control logic circuits and one or more image processing modules that are communicatively coupled to said one or more control logic circuits, wherein said ISP, said one or more control logic circuits, and said one or more image processing modules are integrated on a single substrate of said chip:
• communicating, to said one or more processing modules via said one or more control logic circuits, corresponding configuration parameters that are respectively associated with each one of a plurality of data tiles comprising an image as each data tile progresses through the image sensor pipeline, wherein said communicating of said corresponding configuration parameters occurs before said associated each data tile is about to be communicated to said one or more image processing modules;
• and
• processing said each one of said plurality of data tiles by said one or more image processing modules utilizing said corresponding configuration parameters.