US 8,798,226 B2Granted

Pulse output circuit, shift register and electronic equipment

AssigneeSemiconductor Energy Laboratory Co., Ltd.

InventorsSho Nagao, Yoshifumi Tanada, Yutaka Shionoiri, Hiroyuki Miyake

Life of this patent

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Abstract

A driver circuit of a display device, which includes TFTs of a single conductivity type and outputs an output signal with normal amplitude. A pulse is inputted to TFTs 101 and 104 to turn ON the TFTs and a potential of a node α is raised. When the potential of the node α reaches (VDD−VthN), the node α becomes in a floating state. Accordingly, a TFT 105 is turned ON and a potential of an output node is raised as a clock signal becomes High level. On the other hand, a potential of a gate electrode of the TFT 105 is further raised due to an operation of a capacitance means 107 as the potential of the output node is raised, so that the potential of the gate electrode of the TFT 105 becomes higher than (VDD+VthN). Thus, the potential of the output node is raised to VDD without causing a voltage drop due to a threshold voltage of the TFT 105. An output at the subsequent stage is then inputted to a TFT 103 to turn the TFT 103 ON, while the potential of the node α of TFTs 102 and 106 is dropped to turn the TFT 105 OFF. As a result, the potential of the output node becomes Low level.

Claims14

Dependent claims

A semiconductor device comprising:

a first transistor comprising a first gate, a first source, and a first drain;
a second transistor comprising a second gate, a second source, and a second drain;
a third transistor comprising a third gate, a third source, and a third drain;
a fourth transistor comprising a fourth gate, a fourth source, and a fourth drain;
a fifth transistor comprising a fifth gate, a fifth source, and a fifth drain;
a sixth transistor comprising a sixth gate, a sixth source, and a sixth drain;
a seventh transistor comprising a seventh gate, a seventh source, and a seventh drain;
and
an eighth transistor comprising an eighth gate, an eighth source, and an eighth drain,
wherein the first gate is electrically connected to a first input terminal,
wherein the first gate is electrically connected to the fourth gate,
wherein one of the first source and the first drain is electrically connected to one of the second source and the second drain,
wherein one of the first source and the first drain is electrically connected to one of the seventh source and the seventh drain,
wherein the second gate is electrically connected to one of the third source and the third drain;
wherein the second gate is electrically connected to one of the fourth source and the fourth drain,
wherein the second gate is electrically connected to the sixth gate,
wherein the second gate is electrically connected to the eighth gate,
wherein the other of the second source and the second drain is electrically connected to a first power source,
wherein the third gate is electrically connected to a second input terminal,
wherein the other of the third source and the third drain is electrically connected to a second power source,
wherein the other of the fourth source and the fourth drain is electrically connected to the first power source,
wherein the fifth gate is electrically connected to the other of the seventh source and the seventh drain,
wherein the fifth gate is electrically connected to one of the eighth source and the eighth drain,
wherein one of the fifth source and the fifth drain is electrically connected to one of the sixth source and the sixth drain,
wherein the other of the fifth source and the fifth drain is electrically connected to a third input terminal,
wherein the other of the sixth source and the sixth drain is electrically connected to the first power source, and
wherein the other of the eighth source and the eighth drain is electrically connected to the first power source.

24 more elements

A semiconductor device comprising:

a first transistor comprising a first gate, a first source, and a first drain;
a second transistor comprising a second gate, a second source, and a second drain;
a third transistor comprising a third gate, a third source, and a third drain;
a fourth transistor comprising a fourth gate, a fourth source, and a fourth drain;
a fifth transistor comprising a fifth gate, a fifth source, and a fifth drain;
a sixth transistor comprising a sixth gate, a sixth source, and a sixth drain;
a seventh transistor comprising a seventh gate, a seventh source, and a seventh drain;
and
an eighth transistor comprising an eighth gate, an eighth source, and an eighth drain,
wherein the first gate is electrically connected to a first input terminal,
wherein the first gate is electrically connected to the fourth gate,
wherein one of the first source and the first drain is electrically connected to one of the second source and the second drain,
wherein one of the first source and the first drain is electrically connected to one of the seventh source and the seventh drain,
wherein the second gate is electrically connected to one of the third source and the third drain,
wherein the second gate is electrically connected to one of the fourth source and the fourth drain,
wherein the second gate is electrically connected to the sixth gate,
wherein the second gate is electrically connected to the eighth gate,
wherein the other of the second source and the second drain is electrically connected to a first power source,
wherein the third gate is electrically connected to a second input terminal,
wherein the other of the third source and the third drain is electrically connected to a second power source,
wherein the other of the fourth source and the fourth drain is electrically connected to the first power source,
wherein the fifth gate is electrically connected to the other of the seventh source and the seventh drain,
wherein the fifth gate is electrically connected to one of the eighth source and the eighth drain,
wherein one of the fifth source and the fifth drain is electrically connected to an output terminal and one of the sixth source and the sixth drain,
wherein the other of the fifth source and the fifth drain is electrically connected to a third input terminal,
wherein the other of the sixth source and the sixth drain is electrically connected to the first power source, and
wherein the other of the eighth source and the eighth drain is electrically connected to the first power source.

24 more elements

Dependencies are inferred from the claim text.

Facts

Application: 13/760,147Filed 6 Feb 2013 · continuation
Priority: JP 2003-01038117 Jan 2003
Published: US 2013/0251091 A126 Sep 2013
Granted: 5 Aug 2014
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

G11C 19/28
Digital stores in which the information is moved stepwise, e.g. shift registers: using semiconductor elements
G11C 19/00
Digital stores in which the information is moved stepwise
G09G 3/3688
Details of drivers for data electrodes: suitable for active matrices only
G09G 2310/0275
Details of driving circuits: details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related…

Family

Application10/756,428Parent of this continuation · filed 14 Jan 2004
Application10/958,568Parent of this continuation · filed 6 Oct 2004
US 6,813,332 B2Parent of this continuation · filed 2 Nov 2004
Application11/467,022Parent of this continuation · filed 24 Aug 2006
US 7,116,748 B2Parent of this continuation · filed 3 Oct 2006
US 2013/0251091 A1Pre-grant publication · published 26 Sep 2013
US 2004/0140839 A1Published application
US 2005/0062515 A1Published application
US 2006/0280279 A1Published application
US 8,798,226 B2This patent

From the US filing history. Foreign family members aren’t listed.