US 8,798,223 B2 · Clock and data recovery unit without an external reference clock

Abstract

A clock and data recovery device receives a serial data stream and produces recovered clock and data signals. The clock and data recovery device operates over a range of frequencies and without use an external reference clock. A reference clock generator supplies a reference clock signal to a clock and data recovery module that uses the reference clock as a tuning or reference signal to produce the recovered clock and recovered data signals. The reference clock generator modifies the reference clock signal so that its frequency corresponds, within a small tolerance, to the data rate of the serial data stream. The reference clock generator determines a beat frequency between a voltage-controlled oscillator clock signal and the data rate and adjusts the voltage-controlled oscillator frequency, from which the reference clock is generated, to lower the beat frequency below a divided down version of the voltage-controlled oscillator clock.

Claims26

Dependent claims

A clock and data recovery device, comprising:

reference clock generator circuitry configured to receive a serial data signal and to produce a first clock signal oscillating at a frequency substantially a sub-harmonic of a data rate of the serial data signal without utilizing an external reference clock signal;
and
clock and data recovery circuitry configured to receive the serial data signal and the first clock signal and produce the data output signal representing data recovered from the serial data signal and the second clock signal that is synchronous with the data output signal,
wherein the reference clock generator circuitry comprises:
an oscillator configured to supply a third clock signal oscillating at a controlled frequency, wherein the reference clock generator circuitry utilizes the third clock signal to produce the first clock signal;
a beat frequency generator configured to receive the serial data signal and the third clock signal and produce a beat frequency indicator indicating a difference between the data rate of the serial input signal and the frequency of the third clock signal;
a first divider configured to receive the third clock signal and produce an output signal at a lower frequency;
and
a frequency difference detector configured to compare a frequency of the output signal of the first divider and the beat frequency indicator and produce a frequency comparison indicator.

6 more elements

A clock and data recovery device, comprising:

reference clock generator circuitry configured to receive a serial data signal and to produce a first clock signal oscillating at a frequency substantially proportional to a data rate of the serial data signal without utilizing an external reference clock signal;
and
clock and data recovery circuitry configured to receive the serial data signal and the first clock signal and produce a data output signal representing data recovered from the serial data signal and a second clock signal that is synchronous with the data output signal;
wherein the reference clock generator circuitry comprises:
an oscillator configured to supply a third clock signal oscillating at a controlled frequency, wherein the reference clock generator circuitry utilizes the third clock signal to produce the first clock signal;
a beat frequency generator configured to receive the serial data signal and the third clock signal and produce a beat frequency indicator indicating a difference between the data rate of the serial input signal and the frequency of the third clock signal;
a first divider configured to receive the third clock signal and produce an output signal at a lower frequency;
and
a frequency difference detector configured to compare a frequency of the output signal of the first divider and the beat frequency indicator and produce a frequency comparison indicator;
and
wherein the beat frequency indicator comprises:
a fast difference signal oscillating at a frequency substantially proportional to the frequency of the third clock signal minus the data rate of the serial data signal when the frequency of the third clock signal is higher than the data rate of the serial data signal;
and
a slow difference signal oscillating at a frequency substantially proportional to the data rate of the serial data signal minus the frequency of the third clock signal when the frequency of the data rate of the serial data signal is higher than the third clock signal.

11 more elements

A clock and data recovery device, comprising:

reference clock generator circuitry configured to receive a serial data signal and to produce a first clock signal oscillating at a frequency substantially a sub-harmonic of a data rate of the serial data signal without utilizing an external reference clock signal;
and
clock and data recovery circuitry configured to receive the serial data signal and the first clock signal and produce a data output signal representing data recovered from the serial data signal and a second clock signal that is synchronous with the data output signal;
wherein the reference clock generator circuitry comprises:
an oscillator configured to supply a third clock signal oscillating at a controlled frequency, wherein the reference clock generator circuitry utilizes the third clock signal to produce the first clock signal;
a beat frequency generator configured to receive the serial data signal and the third clock signal and produce a beat frequency indicator indicating a difference between the data rate of the serial input signal and the frequency of the third clock signal;
a first divider configured to receive the third clock signal and produce an output signal at a lower frequency;
and
a frequency difference detector configured to compare a frequency of the output signal of the first divider and the beat frequency indicator and produce a frequency comparison indicator;
and
wherein the frequency comparison indicator comprises:
an up comparison signal that signals that the frequency of the third clock signal is less than the data rate of the serial data signal;
and
a down comparison signal that signals that the frequency of the third clock signal is greater than the data rate of the serial data signal.

11 more elements

A reference clock generator device, comprising:

a controlled oscillator configured to supply a first clock signal oscillating at a controlled frequency and utilized to produce a reference clock signal;
a beat frequency generator configured to receive a serial data signal and the first clock signal and produce a beat frequency indicator indicating a difference between the data rate of the serial data signal and the frequency of the first clock signal;
a first divider configured to receive the first clock signal and produce an output signal at a lower frequency;
a second divider configured to receive the first clock signal and produce the reference clock signal at a lower frequency;
and
a frequency difference detector configured to compare a frequency of the output signal of the first divider and the beat frequency indicator and produce a frequency comparison indicator.

3 more elements

A method for use in recovering clock and data from a serial input signal, comprising:

generating a variable clock signal oscillating at a frequency;
dividing down the variable clock signal to produce a feedback clock signal oscillating at a lower frequency than the frequency of the variable clock signal;
generating a beat frequency indicator indicating a difference between a data rate of the serial input signal and the frequency of the variable clock signal;
comparing the frequency of the feedback clock signal to the beat frequency indicator to produce a frequency comparison indicator;
and
conditionally adjusting the frequency of the variable clock signal based on the frequency comparison indicator, wherein conditionally adjusting the frequency of the variable clock signal comprises adjusting the frequency of the variable clock signal when the frequency comparison indicator indicates that a magnitude of the beat frequency indicator is greater than the frequency of the feedback clock signal.

3 more elements

Dependencies are inferred from the claim text.

Clock and data recovery unit without an external reference clock

Life of this patent

Clock and data recovery unit without an external reference clock

Life of this patent

Abstract

Claims26