Back to results
US 8,798,222 B2Granted
Methods and apparatus for digital linearization of an analog phase interpolator
AssigneeAgere Systems Inc.
InventorsMohammad S. Mobin, Gregory W. Sheets, Lane A. Smith, Craig B. Ziemer
Life of this patent
Estimating the term…
Abstract
Methods and apparatus are provided for digital linearization of an analog phase interpolator. Up to 2N desired phase values are mapped to a corresponding M bit value, where M is greater than N. A corresponding M bit value is applied to the phase interpolator to obtain a desired one of the 2N desired phase values. A linearized phase interpolator is also provided that accounts for process, voltage, temperature or aging (PVTA) variations.
Claims15
A method for linearizing a phase interpolator, comprising:
- obtaining a mapping of up to 2N desired phase values to a corresponding M bit value, wherein a subset of said M bit values are mapped to a corresponding N bit value;
- identifying an M bit value corresponding to a desired phase value;
- determining an N bit value that is mapped to said identified M bit value, where M is a value greater than N;
- applying said determined N bit value to a selector indexed by said N bit value to obtain said identified M bit value;
- and applying said identified M bit value to said phase interpolator to obtain said desired one of said 2N desired phase values wherein said phase interpolator is an over-sampled phase interpolator;
- wherein said obtaining step further comprises the step of evaluating a plurality of phases of an interpolated clock signal generated by said phase interpolator as a function of a plurality of applied interpolation control codes.
3 more elements
A linearized phase interpolator, comprising:
- a plurality of storage elements each storing an M bit value corresponding to one of up to 2N desired phase values, where M is a value greater than N, wherein a subset of said M bit values are mapped to a corresponding N bit value;
- and a selector indexed by an N bit value for selecting one of said storage elements storing a particular M bit value corresponding to a desired one of said 2N desired phase values, wherein said selected corresponding M bit value is applied to a control input of said linearized phase interpolator to obtain a said desired one of said 2N desired phase values, wherein said phase interpolator is an over-sampled phase interpolator;
- wherein said M bit values are obtained by evaluating a plurality of phases of an interpolated clock signal generated by said phase interpolator as a function of a plurality of applied interpolation control codes.
An integrated circuit, comprising:
- a linearized phase interpolator, comprising:
- a plurality of storage elements each storing an M bit value corresponding to one of up to 2N desired phase values, where M is a value greater than N, wherein a subset of said M bit values are mapped to a corresponding N bit value;
- and a selector indexed by an N bit value for selecting one of said storage elements storing a particular M bit value corresponding to a desired one of said 2N desired phase values, wherein said selected corresponding M bit value is applied to a control input of said linearized phase interpolator to obtain a said desired one of said 2N desired phase values, wherein said phase interpolator is an over-sampled phase interpolator;
- wherein said M bit values are obtained by evaluating a plurality of phases of an interpolated clock signal generated by said phase interpolator as a function of a plurality of applied interpolation control codes.
1 more element
Dependencies are inferred from the claim text.