US 8,798,220 B2 · Signal source synchronization circuit · patentgrep

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Abstract

A signal source synchronization circuit includes: a first TDC circuit that measures a first path delay time which is a time difference between an input time of a trigger signal to a first input terminal and an input time of the trigger signal to a second input terminal; and a second TDC circuit that measures a second path delay time which is a time difference between an input time of the trigger signal to a first input terminal and an input time of the trigger signal to a second input terminal, wherein a first phase shifter adjustment circuit sets a phase adjustment amount corresponding to the first path delay time in a first phase shifter, and a second phase shifter adjustment circuit sets a phase adjustment amount corresponding to the second path delay time in a second phase shifter.

Claims18

Dependent claims

A signal source synchronization circuit comprising:

a reference signal source that generates a reference signal;
a first signal source circuit that adjusts a phase of the reference signal generated by the reference signal source and generates a signal synchronized with the reference signal after the phase adjustment;
a second signal source circuit that adjusts a phase of the reference signal generated by the reference signal source and generates a signal synchronized with the reference signal after the phase adjustment;
a trigger signal generation circuit that outputs a trigger signal;
a first time difference measurement circuit that has a first input terminal to which the trigger signal outputted from the trigger signal generation circuit is directly inputted and a second input terminal to which the trigger signal outputted from the trigger signal generation circuit and then fed back via the first signal source circuit is inputted, and measures a time difference between an input time of the trigger signal to the first input terminal and an input time of the trigger signal to the second input terminal;
and
a second time difference measurement circuit that has a first input terminal to which the trigger signal outputted from the trigger signal generation circuit is directly inputted and a second input terminal to which the trigger signal outputted from the trigger signal generation circuit and then fed back via the second signal source circuit is inputted, and measures a time difference between an input time of the trigger signal to the first input terminal and an input time of the trigger signal to the second input terminal, wherein
the first signal source circuit adjusts the phase of the reference signal according to the time difference measured by the first time difference measurement circuit, and
the second signal source circuit adjusts the phase of the reference signal according to the time difference measured by the second time difference measurement circuit.

6 more elements

A signal source synchronization circuit comprising:

a reference signal source that generates a reference signal;
a first signal source circuit that adjusts a phase of the reference signal generated by the reference signal source and generates a signal synchronized with the reference signal after the phase adjustment;
a second signal source circuit that adjusts a phase of the reference signal generated by the reference signal source and generates a signal synchronized with the reference signal after the phase adjustment;
a trigger signal generation circuit that outputs a trigger signal;
and
a time difference measurement circuit that is implemented in the first signal source circuit, has a first input terminal to which the trigger signal outputted from the trigger signal generation circuit is directly inputted and a second input terminal to which the trigger signal outputted from the trigger signal generation circuit and inputted to the first signal source circuit, and then fed back via the second signal source circuit is inputted, and measures a time difference between an input time of the trigger signal to the first input terminal and an input time of the trigger signal to the second input terminal, wherein
the second signal source circuit adjusts the phase of the reference signal according to the time difference measured by the time difference measurement circuit.

4 more elements

A signal source synchronization circuit comprising:

a reference signal source that generates a reference signal;
a first signal source circuit that adjusts a phase of the reference signal generated by the reference signal source and generates a signal synchronized with the reference signal after the phase adjustment;
a second signal source circuit that adjusts a phase of the reference signal generated by the reference signal source and generates a signal synchronized with the reference signal after the phase adjustment;
a first time difference measurement circuit that has a first input terminal to which the reference signal generated by the reference signal source is directly inputted and a second input terminal to which the reference signal generated by the reference signal source and then fed back via the first signal source circuit is inputted, and measures a time difference between an input time of the reference signal to the first input terminal and an input time of the reference signal to the second input terminal;
and
a second time difference measurement circuit that has a first input terminal to which the reference signal generated by the reference signal source is directly inputted and a second input terminal to which the reference signal generated by the reference signal source and then fed back via the second signal source circuit is inputted, and measures a time difference between an input time of the reference signal to the first input terminal and an input time of the reference signal to the second input terminal, wherein
the first signal source circuit adjusts the phase of the reference signal according to the time difference measured by the first time difference measurement circuit, and
the second signal source circuit adjusts the phase of the reference signal according to the time difference measured by the second time difference measurement circuit.

5 more elements

A signal source synchronization circuit comprising:

a reference signal source that generates a reference signal;
a first signal source circuit that adjusts a phase of the reference signal generated by the reference signal source, and generates a signal synchronized with the reference signal after the phase adjustment, and that also outputs the reference signal before the phase adjustment after holding the reference signal before the phase adjustment in a first buffer circuit for a first delay time;
a second signal source circuit that holds the reference signal outputted from the first signal source circuit in a second buffer circuit for a second delay time, then adjusts a phase of the reference signal, and generates a signal synchronized with the reference signal after the phase adjustment;
a first time difference measurement circuit that is implemented in the first signal source circuit, has a first input terminal to which the reference signal generated by the reference signal source is directly inputted and a second input terminal to which the reference signal generated by the reference signal source and inputted to the first signal source circuit, and then fed back via the second signal source circuit is inputted, and measures a time difference between an input time of the reference signal to the first input terminal and an input time of the reference signal to the second input terminal;
and
a second time difference measurement circuit that is implemented in the second signal source circuit, has a first input terminal to which the reference signal generated by the reference signal source and transmitted via the first signal source circuit without being held in the first buffer circuit for the first delay time is inputted and a second input terminal to which the reference signal generated by the reference signal source and then transmitted after being held in the first and second buffer circuits for the first and second delay times is inputted, and measures a time difference between an input time of the reference signal to the first input terminal and an input time of the reference signal to the second input terminal, wherein
the first signal source circuit adjusts the phase of the reference signal according to the time difference measured by the first time difference measurement circuit, and
the second signal source circuit adjusts the phase of the reference signal according to the time difference measured by the second time difference measurement circuit.

5 more elements

A signal source synchronization circuit comprising:

a reference signal source that generates a reference signal;
a trigger signal generation circuit that outputs a trigger signal;
a first signal source circuit that adjusts a phase of the reference signal generated by the reference signal source, and generates a signal synchronized with the reference signal after the phase adjustment, while outputting the trigger signal outputted from the trigger signal generation circuit after holding the trigger signal in a first buffer circuit for a first delay time;
a second signal source circuit that adjusts a phase of the reference signal generated by the reference signal source, and generates a signal synchronized with the reference signal after the phase adjustment, while outputting the trigger signal outputted from the first signal source circuit after holding the trigger signal in a second buffer circuit for a second delay time;
a first time difference measurement circuit that is implemented in the first signal source circuit, has a first input terminal to which the trigger signal outputted from the trigger signal generation circuit is directly inputted and a second input terminal to which the trigger signal outputted from the trigger signal generation circuit, inputted to the first signal source circuit, and then fed back via the second signal source circuit is inputted, and measures a time difference between an input time of the trigger signal to the first input terminal and an input time of the trigger signal to the second input terminal;
and
a second time difference measurement circuit that is implemented in the second signal source circuit, has a first input terminal to which the trigger signal outputted from the trigger signal generation circuit and then transmitted via the first signal source circuit without being held in the first buffer circuit for the first delay time is inputted and a second input terminal to which the trigger signal outputted from the trigger signal generation circuit and then transmitted after being held in the first and second buffer circuits for the first and second delay times is inputted, and measures a time difference between an input time of the trigger signal to the first input terminal and an input time of the trigger signal to the second input terminal, wherein
the first signal source circuit adjusts the phase of the reference signal according to the time difference measured by the first time difference measurement circuit, and
the second signal source circuit adjusts the phase of the reference signal according to the time difference measured by the second time difference measurement circuit.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 13/860,957Filed 11 Apr 2013
Priority: JP 2012-9996225 Apr 2012
Published: US 2013/0287155 A131 Oct 2013
Granted: 5 Aug 2014
Term ends: Not estimatedThe source records don’t support an estimate.

Classification5 codes

H04L 7/0079
Arrangements for synchronising receiver with transmitter: receiver details
G06F 1/10
Generating or distributing clock signals or signals derived directly therefrom: distribution of clock signals , e.g. skew
G06F 1/12
Generating or distributing clock signals or signals derived directly therefrom: synchronisation of different clock signals provided by a plurality…
H04L
Digital communication

Family

US 2013/0287155 A1Pre-grant publication · published 31 Oct 2013
US 8,798,220 B2This patent

From the US filing history. Foreign family members aren’t listed.

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