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US 8,798,217 B2Granted
Method and digital circuit for recovering a clock and data from an input signal using a digital frequency detection
AssigneeQUALCOMM Incorporated
InventorsXiaohua Kong, Zhi Zhu, Nam V. Dang, Tirdad Sowlati
Life of this patent
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Abstract
In a particular embodiment, a digital circuit includes a frequency detection circuit operative to compare information related to transitions between sequential samples of a received signal. The frequency detection circuit is further operative to generate a control signal to reduce a sampling rate of the received signal in response to a predetermined number of the sequential samples having a same value. The digital circuit also includes a digital phase detector operative to provide the information related to the transitions between sequential samples to the frequency detection circuit.
Claims47
A method, comprising:
- in response to a first predetermined number of consecutive signal samples of a received signal having a same bit value, reducing a sampling rate frequency of the received signal;
- and
- in response to a second predetermined number of consecutive signal samples of the received signal having alternating bit values, increasing the sampling rate frequency of the received signal, wherein information related to transitions between sample values of the received signal is received from a digital phase detector.
An apparatus comprising:
- a frequency detection circuit operative to compare information related to transitions between consecutive signal samples of a received signal and to generate a first control signal to reduce a sampling rate frequency of the received signal in response to a first predetermined number of the consecutive signal samples having a same bit value, wherein the frequency detection circuit is further operative to generate a second control signal to increase the sampling frequency of the received signal in response to a second predetermined number of consecutive signal samples of the received signal having alternating bit values;
- and
- a digital phase detector operative to provide the information related to the transitions between consecutive signal samples to the frequency detection circuit.
A method comprising:
- reducing a sampling rate frequency of a received signal by a frequency detection circuit in response to a first predetermined number of consecutive signal samples of the received signal having a same bit value;
- increasing the sampling rate frequency of the received signal by the frequency detection circuit in response to a second predetermined number of consecutive signal samples of the received signal having alternating bit values;
- detecting a clock and data recovery (CDR) lock-in of the received signal;
- and
- selectively disabling the frequency detection circuit in response to detecting the CDR lock-in.
2 more elements
An apparatus comprising:
- a frequency detection circuit operative to compare consecutive signal samples of a received signal and to generate a first control signal to reduce a sampling rate frequency of the received signal in response to a first predetermined number of the consecutive signal samples having a same bit value, wherein the frequency detection circuit is further operative to generate a second control signal to increase the sampling frequency of the received signal in response to a second predetermined number of consecutive signal samples of the received signal having alternating bit values;
- and
- a deserializer operative to provide the consecutive signal samples of the received signal as parallel data to the frequency detection circuit.
An apparatus comprising:
- means for comparing consecutive signal samples of a received signal;
- means for generating a first control signal in response to a first predetermined number of the consecutive signal samples having a same bit value;
- means for generating a second control signal in response to a second predetermined number of the consecutive signal samples having alternating bit values;
- and
- means for providing information related to transitions between sample values to the means for comparing, wherein the first control signal indicates a sampling rate frequency of the received signal is too fast, and wherein the second control signal indicates the sampling rate frequency is too slow.
2 more elements
A method comprising:
- a step for determining whether a first predetermined number of consecutive signal samples of a received signal have a same bit value;
- a step for reducing a sampling rate frequency of the received signal in response to the first predetermined number of consecutive signal samples having the same bit value, wherein information related to transitions between sample values of the received signal is received from a digital phase detector;
- a step for determining whether a second predetermined number of consecutive signal samples of the received signal have alternating bit values;
- and
- a step for increasing the sampling frequency of the received signal in response to the second predetermined number of consecutive signal samples of the received signal having alternating bit values.
2 more elements
A non-transient computer readable tangible medium storing instructions executable by a computer, the instructions comprising:
- instructions executable by the computer to reduce a sampling rate frequency of a received signal in response to a first predetermined number of consecutive signal samples of the received signal having a same bit value;
- and
- instructions executable by the computer to increase the sampling rate frequency of the received signal in response to a second predetermined number of consecutive signal samples of the received signal having alternating bit values, wherein information related to transitions between sample values of the received signal is received from a digital phase detector.
A method comprising:
- receiving a data file comprising design information corresponding to a semiconductor device;
- and
- fabricating the semiconductor device according to the design information, wherein the semiconductor device comprises:
- a frequency detection circuit operative to compare consecutive signal samples of a received signal, and to generate a control signal to reduce a sampling rate frequency of the received signal in response to a first predetermined number of the consecutive signal samples having a same bit value,
- wherein the frequency detection circuit is further operative to generate a second control signal to increase the sampling frequency of the received signal in response to a second predetermined number of consecutive signal samples of the received signal having alternating bit values;
- and
- a digital phase detector operative to provide information related to transitions between sample values to the frequency detection circuit.
4 more elements
Dependencies are inferred from the claim text.