Apparatus and method for detecting code
AssigneeElectronics and Telecommunications Research Institute
InventorsEun Jeong Shin, Dae Ho Kim
Life of this patent
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Abstract
Disclosed is an apparatus and method for detecting a code. The code detecting apparatus may include a detector to detect symbol synchronous timing information associated with a PSS code from a first signal received during a predetermined first period, a compensator to extract and buffer the PSS code and the SSS code based on the symbol synchronous timing information detected from a second signal received during a predetermined second period, and compensate for a frequency offset with respect to the buffered PSS code, and a processor to re-detect the symbol synchronous timing information based on the PSS code in which the frequency offset is compensated for, and extract the buffered SSS code using the re-detected symbol synchronous timing information.
Claims8
An apparatus for detecting a code, the apparatus comprising:
- a detector to detect symbol synchronous timing information associated with a primary synchronization signal (PSS) code from a first signal received during a predetermined first period;
- a compensator to extract and buffer the PSS code and a secondary synchronization signal (SSS) code based on the detected symbol synchronous timing information detected from a second signal received during a predetermined second period subsequent to the first period, and compensate for a frequency offset of the buffered PSS code;
- and
- a processor to re-detect the symbol synchronous timing information based on the PSS code in which the frequency offset is compensated for, and extract the buffered SSS code using the re-detected symbol synchronous timing information.
A method for detecting a code, the method comprising:
- detecting symbol synchronous timing information associated with a primary synchronization signal (PSS) code from a first signal received during a predetermined first period;
- extracting and buffering the PSS code and a secondary synchronization signal (SSS) code based on the detected symbol synchronous timing information from a second signal received during a predetermined second period subsequent to the first period, and compensating for a frequency offset of the buffered PSS code;
- re-detecting the symbol synchronous timing information based on the PSS code in which the frequency offset is compensated for;
- and
- extracting the buffered SSS code using the re-detected symbol synchronous timing information.
Dependencies are inferred from the claim text.