Digital video physical layer using a multi-level data code

A method comprising the steps of:

• (a) transmitting a clock signal at a predetermined rate;
• and
• (b) transmitting data as a sequence of blocks of multi-level symbols at a fixed multiple of the clock rate;
• (c) wherein each block of multi-level symbols comprises a sequence of at least three multi-level symbols;
• (d) wherein each multi-level symbol has an analog voltage level selected from a predetermined number of possible values, the predetermined number being an odd integer greater than two;
• (e) wherein the fixed multiple of the clock rate is an integer greater than one;
• and
• (f) wherein each block of multi-level symbols to the code defined in Table 2.

A method comprising the steps of:

• (a) deriving a code block for each of a plurality of signals in accordance with a predetermined code by an encoder;
• (b) accepting the code block from the encoder and generating, as an output, a group of multi-level symbols corresponding thereto by a digital to analog converter;
• (c) transmitting the group of multi-level symbols over at least one data channel;
• (d) accepting, as an input, the group of multi-level symbols and generating the code block corresponding thereto by an analog to digital converter;
• and
• (e) accepting the code block from the analog to digital converter and deriving each of the plurality of signals from the code block in accordance with the predetermined code by a decoder;
• (f) wherein each multi-level symbol has an analog voltage level selected from a predetermined number of possible values, the predetermined number being an odd integer greater than two;
• and
• (g) wherein the code block is encoded using the code defined in Table 2.

A method for transmitting data and control signals on twisted wire pairs, the method comprising:

• (a) providing a clock channel operating at a predetermined rate and transmitting a clock signal on a first one of the twisted wire pairs;
• (b) providing at least one data channel, each operating at a same fixed multiple of the clock rate;
• and
• (c) wherein each of the at least one data channel includes:
• (i) an encoder performing the steps of:
• (A) accepting, as an input set, a transition minimized differential signaling (TMDS) “Data Enable” signal, two TMDS control signals, “[C1:C0]”, and eight TMDS data signals, “[D7:D0]”,
• (B) producing, as an output set, a first sequence of three undenary symbols, and
• (C) computing a running digital sum of the undenary symbols of the first sequence,
• (ii) a digital to analog converter for accepting the first sequence of three undenary symbols and producing therefrom an output varying level analog voltage in synchronization with the clock channel,
• (iii) a pre-emphasis stage for conditioning and transmitting the varying level analog voltage onto a corresponding further one of the twisted wire pairs,
• (iv) an equalization stage for receiving and conditioning the varying level analog voltage from the corresponding further one of the twisted wire pairs,
• (v) an analog to digital converter for accepting the varying level analog voltage and producing therefrom a second sequence of three undenary symbols in synchronization with the clock channel,
• (vi) a decoder performing the steps of:
• (A) accepting, as an input set, the second sequence of three undenary symbols, and
• (B) producing, as an output set, a TMDS “Data Enable” signal, two TMDS control signals, “[CI:C0]”, and eight TMDS data signals, “[D7:D0]”.