Implementing SDRAM having no RAS to CAS delay in write operation
AssigneeInternational Business Machines Corporation
InventorsBrian J. Connolly, Kyu-hyoun Kim, Warren E. Maule
Life of this patent
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Abstract
A method and circuit for implementing faster-cycle-time and lower-energy write operations for Synchronous Dynamic Random Access Memory (SDRAM), and a design structure on which the subject circuit resides are provided. A first RAS (row address strobe) to CAS (column address strobe) command delay (tRCD) is provided to the SDRAM for a read operation. A second delay tRCD is provided for a write operation that is substantially shorter than the first delay tRCD for the read operation.
Claims19
A circuit for implementing faster-cycle-time and lower-energy write operations for Synchronous Dynamic Random Access Memory (SDRAM) comprising:
- a memory controller coupled to the SDRAM;
- said memory controller providing a first RAS (row address strobe) to CAS (column address strobe) command delay (tRCD) to the SDRAM for a read operation;
- and
- said memory controller providing a second delay tRCD for a write operation;
- said second delay tRCD being substantially shorter than said first delay tRCD for said read operation.
A design structure embodied in a machine readable medium used in a design process, the design structure comprising:
- a circuit tangibly embodied in the machine readable medium used in the design process, said circuit for implementing faster-cycle-time and lower-energy write operations for Synchronous Dynamic Random Access Memory (SDRAM), said circuit comprising:
- a memory controller coupled to the SDRAM;
- said memory controller providing a first RAS (row address strobe) to CAS (column address strobe) command delay (tRCD) to the SDRAM for a read operation;
- and
- said memory controller providing a second delay tRCD for a write operation;
- said second delay tRCD being substantially shorter than said first delay tRCD for said read operation.
A method for implementing faster-cycle-time and lower-energy write operations for Synchronous Dynamic Random Access Memory (SDRAM) comprising:
- providing a first RAS (row address strobe) to CAS (column address strobe) command delay (tRCD) to the SDRAM for a read operation;
- and
- providing a second delay tRCD for a write operation;
- said second delay tRCD being substantially shorter than said first delay tRCD for said read operation.
Dependencies are inferred from the claim text.