Card controller controlling semiconductor memory including memory cell having charge accumulation layer and control gate
AssigneeKabushiki Kaisha Toshiba
InventorHidetaka Tsuji
Life of this patent
Estimating the term…
Abstract
A card controller includes an arithmetic processing device. The controller writes data to a semiconductor memory having a first memory block and a second memory block each including a plurality of nonvolatile memory cells each configured to hold at least 2 bits, data in the first memory block and data in the second memory block being each erased at a time. The arithmetic processing device writes the data to the memory cells in the first memory block using an upper bit and a lower bit of the at least 2 bits and writes the data to the memory cells in the second memory block using only the lower bit of the at least 2 bits.
Claims20
A controller comprising:
- an interface configured to execute interfacing process with a host apparatus;
- and
- a processor configured to control a memory, the memory including a first memory block and a second memory block, the first memory block and the second memory block including memory cells each capable of holding i-bit data (where i is natural number greater than or equal to 2),
- wherein the processor instructs the memory to write first data received from the host apparatus in the first memory block such that the memory cells written with the first data in the first memory block each store j-bit data (where j is natural number lower than i);
- and
- the processor instructs the memory to copy the first data in the first memory block to the second memory block such that the memory cells written with the first data in the second memory block each store k-bit data (where k is natural number lower than i).
A controller comprising:
- an interface configured to execute interfacing process with a host apparatus;
- and
- a processor configured to control a memory, the memory including a first memory block and a second memory block, the first memory block and the second memory block including memory cells each capable of holding i-bit data (where i is natural number greater than or equal to 2),
- wherein the processor instructs the memory to write first data received from the host apparatus in the first memory block such that the memory cells written with the first data in the first memory block each store j-bit data (where j is natural number lower than i);
- the processor instructs the memory to write second data received from the host apparatus in the first memory block such that the memory cells written with the second data in the first memory block each store j-bit data, the second data updating the first data written in the first memory block;
- and
- the processor instructs the memory to copy the second data in the first memory block to the second memory block such that the memory cells written with the second data in the second memory block each store k-bit data (where k is natural number lower than i).
Dependencies are inferred from the claim text.