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US 8,797,819 B2Granted
Refreshing data of memory cells with electrically floating body transistors
AssigneeMicron Technology, Inc.
InventorsEric Carman, Mikhail Nagoga, Serguei Okhonin
Life of this patent
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Abstract
A semiconductor device along with circuits including the same and methods of operating the same are described. The device comprises a memory cell including one transistor. The transistor comprises a gate, an electrically floating body region, and a source region and a drain region adjacent the body region. Data stored in memory cells of the device can be refreshed within a single clock cycle.
Claims20
An integrated circuit device comprising:
- a plurality of memory cells each comprising a transistor having a body region configured to be electrically floating for storing data;
- and
- refresh circuitry coupled to the plurality of memory cells, the refresh circuitry configured to refresh data stored in each transistor by reading the data from the transistor and writing the data to the transistor during a single clock cycle with no intervening hold state therebetween.
An integrated circuit device comprising:
- a plurality of memory cells each comprising a transistor having a gate, a body region configured to be electrically floating for storing data, and a source region and a drain region adjacent the body region;
- and
- refresh circuitry coupled to the plurality of memory cells, the refresh circuitry configured to refresh data stored in each transistor by reading the data from the transistor and writing the data to the transistor during a single clock cycle with no intervening hold state therebetween.
Dependencies are inferred from the claim text.