Semiconductor devices, operating methods thereof, and memory systems including the same

An operating method of a semiconductor device, the operating method comprising:

• selectively providing a power supply voltage to a first sense amplifier selectively connected between a first bit line and a second bit line using a first power supply circuit which operates in response to a first control signal;
• selectively providing a ground voltage to a second sense amplifier selectively connected between the first bit line and the second bit line using a second power supply circuit which operates in response to a second control signal;
• controlling a connection between the first power supply circuit and the second power supply circuit using a switching circuit which operates in response to a third control signal;
• and
• generating the first control signal and the third control signal during a data flip period, the first control signal and the third control signal being complementary to each other.

A semiconductor device comprising:

• a control signal generation circuit configured to generate at least one control signal, the control signal generation circuit including first, second and third control signal generators, the first, second and third control signal generators configured to provide first, second and third control signals, respectively;
• and
• at least one sense amplifier including first and second power supply circuits and configured to selectively connect the first and second power supply circuits based on the at least one control signal,
• the first power supply circuit configured to provide a power supply voltage based on the first control signal,
• the second power supply circuit configured to provide a ground voltage based on the second control signal, and
• the at least one sense amplifier configured to selectively connect the first and second power supply circuits based on the third control signal, wherein
• the first control signal generator is configured to provide the first control signal based on block information, a sense amplifier enable signal and a write flip signal, the write flip signal indicating an activated first control signal and a deactivated third control signal during a data flip period,
• the second control signal generator is configured to provide the second control signal based on the block information and the sense amplifier enable signal, and
• the third control signal generator is configured to provide the third control signal based on the write flip signal, the write enable signal and command execution mode information, the command execution mode information indicates a read or write command.