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US 8,797,816 B2Granted
Semiconductor memory apparatus and bit line equalizing circuit
AssigneeSK hynix Inc.
InventorMi Hyeon Jo
Life of this patent
Estimating the term…
Abstract
A semiconductor memory apparatus comprises bit line sense amplifier unit, and a pair of precharge elements coupled in series between a first bit line and a second bit line and having an asymmetrical contact resistance ratio.
Claims14
A semiconductor memory apparatus comprising a first bit line sense amplifier unit coupled between a first bit line and a second bit line;
- and
- a pair of precharge elements coupled in series between the first bit line and the second bit line and having an asymmetrical contact resistance ratio,
- wherein the pair of precharge elements comprises a first precharge element and a second precharge element, and
- the contact resistance ratio is set so that a first charge time and a second charge time are equalized to each other,
- wherein the first charge time is decided by a first contact resistance of the first precharge element coupled to the first bit line, and a capacitance existing in the first bit line, and
- the second charge time is decided by a second resistance of the second precharge element coupled to the second bit line, and a capacitance existing in the second bit line.
3 more elements
A bit line equalizing circuit which is coupled between first and second bit lines, and precharges the first and second bit lines to a preset voltage, the bit line equalizing circuit comprising:
- a first precharge element coupled between the first bit line and a first precharge voltage supply line and driven in response to a bit line equalize signal;
- and
- a second precharge element coupled between a second precharge voltage supply line and the second bit line and driven in response to the bit line equalize signal,
- wherein a ratio of a resistance value between the first bit line and the first precharge voltage supply line and a resistance value between the second bit line and the second precharge voltage supply line is set so that a first charge time and a second charge time are equalized to each other,
- wherein the first charge time is decided by a first contact resistance of the first precharge element coupled to the first bit line, and a capacitance existing in the first bit line, and
- the second charge time is decided by a second resistance of the second precharge element coupled to the second bit line, and a capacitance existing in the second bit line.
3 more elements
Dependencies are inferred from the claim text.