Method and apparatus to reduce power consumption by transferring functionality from memory components to a memory interface
AssigneeQimonda AG
InventorJong-Hoon Oh
Life of this patent
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AssigneeQimonda AG
InventorJong-Hoon Oh
Estimating the term…
A common Delay Locked Loop (DLL) circuit and/or voltage generator circuit is provided in, or associated with. a memory interface interposed between a memory controller and a plurality of memory components. Corresponding circuits in the memory components are disabled and/or bypassed, or the memory components are manufactured without the circuits. Both the DLL circuit and voltage generator draw current, which is multiplied by the number of memory components in a memory system. By operating a single DLL circuit and/or voltage generator in or associated with the memory interface, that generates a read clock signal and/or various voltage levels, respectively, for all memory components in the memory system, power consumption may be significantly reduced.
A method of performing a memory read operation by a memory interface interposed between a memory controller and a plurality of memory components, comprising:
A synchronous memory system, comprising:
A synchronous memory system, comprising:
Dependencies are inferred from the claim text.