Semiconductor integrated circuit with thick gate oxide word line driving circuit

A semiconductor integrated circuit comprising:

• a memory cell array including:
• a pair of bit lines (DT/DB);
• a plurality of word lines (WL), and
• a plurality of memory cells (MC), each of the plurality of memory cells is coupled to one of the bit lines and to one of the plurality of word lines, and including a first transistor (TTr) having a first gate electrode and a first gate oxide film;
• a plurality of driving circuits (DRV) including a plurality of first driving circuits (10) that are formed in a first region and a plurality of second driving circuits (20) that are formed in a second region, each of the driving circuits including a second transistor (DMP/DMN) having a second gate electrode and a second gate oxide film and alternately providing a first voltage (VPP) and a second voltage (VSS/VKK) lower than the first voltage to the associated one of the word lines, and
• wherein the first gate oxide film is thinner than the second gate oxide film,
• wherein the first voltage (VPP) is applied to the first gate electrode to activate the first transistor, and
• wherein the memory cell array (11) is provided between the first and the second region.

A semiconductor integrated circuit comprising:

• a memory array (11) including:
• pairs of bit lines (DT/DB);
• word lines (WLn);
• memory cells (MCn) each including:
• a capacitor (CC);
• and
• a transistor (TTr) having a gate oxide film, a gate coupled to one of the pairs of bit lines (DT/DB) and a source-drain path coupled between the capacitor (CC) and one of the word lines (WLn);
• and
• driving circuits (DRV) each of which is provided to drive the associated one of the word lines (WLn) and includes a drive transistor (DMP/DMN) having a gate oxide film thicker than that of the gate transistor (TTr), wherein a range of voltage between the gate and back-gate of the gate transistor (TTr) is larger than a voltage range of the bit lines (DT),
• wherein the driving circuits comprise:
• first driving circuits (10) arranged on a first region and,
• second driving circuits (20) arranged on a second region, and
• wherein the memory cell array (11) is arranged between the first region and the second region.