Semiconductor device and semiconductor memory device

A semiconductor device, comprising:

• a non-volatile memory unit;
• a data bus configured to transfer data outputted from the non-volatile memory unit;
• a first selection signal generation unit configured to sequentially enable a plurality of first selection signals in response to a first clock;
• a plurality of first latch sets configured to each be enabled in response to a first selection signal that corresponds to the first latch set among the first selection signals and store the data transferred through the data bus;
• a clock transfer unit configured to transfer the first clock as a second clock after each one of the first selection signals is enabled;
• a second selection signal generation unit configured to sequentially enable a plurality of second selection signals in response to the second clock;
• and
• a plurality of second latch sets configured to each be enabled in response to a second selection signal that corresponds to the second latch set among the multiple second selection signals and store the data transferred through the data bus.

A semiconductor memory device, comprising:

• a non-volatile memory unit configured to store repair data;
• a data bus configured to transfer the data outputted from the non-volatile memory unit;
• a first selection signal generation unit configured to sequentially enable a plurality of first selection signals in response to a first clock;
• a plurality of first latch sets configured to each be enabled in response to a first selection signal that corresponds to the first latch set among the first selection signals and store the data transferred through the data bus;
• a first memory bank configured to replace a normal memory cell with a redundancy memory cell based on the data stored in the first latch sets;
• a clock transfer unit configured to transfer the first clock as a second clock after each one of the first selection signals is enabled;
• a second selection signal generation unit configured to sequentially enable a plurality of second selection signals based on the second clock;
• a plurality of second latch sets configured to each be enabled in response to a second selection signal that corresponds to the second latch set among the multiple second selection signals and store the data transferred through the data bus;
• and
• a second memory bank configured to substitute a normal memory cell with a redundancy memory cell based on the data stored in the second latch sets.

A semiconductor memory device, comprising:

• a non-volatile memory unit configured to store repair data;
• a data bus configured to transfer the data outputted from the non-volatile memory unit;
• a first selection signal generation unit configured to sequentially enable a plurality of first selection signals in response to a first clock;
• a plurality of first latch sets configured to each be enabled in response to a first selection signal that corresponds to the first latch set among the first selection signals and store the data transferred through the data bus;
• a plurality of second latch sets configured to each be enabled in response to a first selection signal that corresponds to the second latch set among the multiple first selection signals and store the data transferred through the data bus;
• a first memory bank configured to replace a normal memory cell with a redundancy memory cell based on the data stored in the first latch sets;
• a second memory bank configured to replace a normal memory cell with a redundancy memory cell based on the data stored in the second latch sets;
• a clock transfer unit configured to transfer the first clock as a second clock after each of the multiple first selection signals is enabled;
• a second selection signal generation unit configured to sequentially enable a plurality of second selection signals in response to the second clock;
• a plurality of third latch sets to each be enabled in response to a second selection signal that corresponds to the third latch set among the multiple second selection signals and store the data transferred through the data bus;
• a plurality of fourth latch sets configured to each be enabled in response to a second selection signal that corresponds to the fourth latch set among the multiple second selection signals and store the data transferred through the data bus;
• a third memory bank configured to replace a normal memory cell with a redundancy memory cell based on the data stored in the third latch sets;
• and
• a fourth memory bank configured to replace a normal memory cell with a redundancy memory cell based on the data stored in the fourth latch sets.