Back to results
US 8,797,807 B2Granted
Semiconductor memory and semiconductor memory control method
AssigneeKabushiki Kaisha Toshiba
InventorsMasahiro Yoshihara, Katsumi Abe
Life of this patent
Estimating the term…
Abstract
According to one embodiment, the semiconductor memory includes a memory cell array which includes memory cells to store data, a buffer circuit which includes latches, each of the latches including transistors as control elements and a flip-flop, and a control circuit which turns off the transistors to deactivate one or more of the latches.
Claims20
A semiconductor memory comprising:
- a memory cell array including memory cells to store data;
- at least one first latch including first transistors and a first flip-flop to hold data;
- at least one second latch including second transistors and a second flip-flop to hold data;
- and
- a control circuit configured to, by turning off the first transistors, deactivate the first latch and maintain the second latch in an active state when a busy/ready signal changes from a first voltage to a second voltage, wherein the second voltage is larger than the first voltage.
2 more elements
A semiconductor memory control method comprising:
- controlling, by a control circuit, input or output of data between a memory cell array, at least one of a first latch and at least one of a second latch, the first latch including first transistors and a first flip-flop, and the second latch including second transistors and a second flip-flop;
- and
- turning off, by the control circuit, the first transistors to deactivate the first latch, wherein the control circuit maintains an active state when a busy/ready signal changes from a first voltage to a second voltage, wherein the second voltage is larger than the first voltage.
Dependencies are inferred from the claim text.