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US 8,797,802 B2Granted
Method and apparatus for shortened erase operation
AssigneeMacronix International Co., Ltd.
InventorsChun-Hsiung Hung, Kuen-Long Chang, Ken-Hui Chen, Nai-Ping Kuo, Chin-Hung Chang, Chang-Ting Chen
Life of this patent
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Abstract
A nonvolatile memory array has a multiple erase procedures of different durations. A block of memory cells of the array can be erased by one of the different erase procedures.
Claims24
An integrated circuit, comprising:
- a nonvolatile memory array with memory cells;
- and
- control circuitry performing a multi-phase erase procedure including an erase phase and one or more phases from a pre-program phase and a soft program phase, the multi-phase erase procedure having characteristics determined by a particular mode that is one of a first erase mode and a second erase mode, the first erase mode having a shorter duration than the second erase mode of performing the multi-phase erase procedure on a block of memory cells in the nonvolatile memory array.
A method of erasing memory cells in a nonvolatile memory array, comprising:
- receiving an erase command identifying a block of memory cells in the nonvolatile memory array;
- and
- responsive to the erase command, performing a multi-phase erase procedure including an erase phase and one or more phases from a pre-program phase and a soft program phase, the multi-phase erase procedure having characteristics determined by a particular mode that is one of a first erase mode and a second erase mode, the first erase mode having a shorter duration on average than the second erase mode of performing the multi-phase erase procedure on the block of memory cells in the nonvolatile memory array.
Dependencies are inferred from the claim text.