Device selection schemes in multi chip package NAND flash memory system
AssigneeConversant Intellectual Property Management Inc.
InventorJin-Ki Kim
Life of this patent
Estimating the term…
Abstract
Systems and methods are provided for perform device selection in multi-chip package NAND flash memory systems. In some embodiments, the memory controller performs device selection by command. In other embodiments, the memory controller performs device selection by input address.
Claims30
A memory system comprising:
- a memory controller;
- a plurality of memory devices connected to the controller via a common bus with a multi-drop connection;
- wherein the memory controller performs device selection by input address;
- each memory device comprising:
- a register containing a device identifier;
- a device identifier comparator that compares selected bits of a received input address to contents of the register to determine if there is a match, and wherein a given device is selected if the device identifier comparator of the given device determines there is a match;
- wherein each memory device further comprises a burst data controller that causes the memory device to be selected:
- when the device identifier comparator determines there is a match;
- while a command input is in progress;
- and
- while an address input is in progress.
A memory system comprising:
- a memory controller;
- a plurality of memory devices connected to the controller via a common bus with a multi-drop connection;
- wherein the memory controller performs device selection by input address;
- each memory device comprising:
- a register containing a device identifier;
- a device identifier comparator that compares selected bits of a received input address to contents of the register to determine if there is a match, and wherein a given device is selected if the device identifier comparator of the given device determines there is a match
- wherein each memory device further comprises:
- a write enable buffer for buffering a received write enable signal, the write buffer having an input for receiving an indication of whether that memory device is selected or deselected, and wherein the write enable buffer is disabled when the memory device is deselected;
- a read enable buffer for buffering a received read enable signal, the read buffer having an input for receiving an indication of whether that memory device is selected or deselected, and wherein the read enable buffer is disabled when the memory device is deselected.
A memory system comprising:
- a memory controller;
- a plurality of memory devices connected to the controller via a common bus with a multi-drop connection;
- wherein the memory controller performs device selection by input address;
- each memory device comprising:
- a register containing a device identifier;
- a device identifier comparator that compares selected bits of a received input address to contents of the register to determine if there is a match, and wherein a given device is selected if the device identifier comparator of the given device determines there is a match;
- wherein the common bus comprises:
- a write protect line;
- a write enable line;
- a read enable line;
- an address latch enable line;
- a command latch enable line;
- a chip enable line;
- an I/O for command, address and data;
- and
- a ready/busy line.
A memory device for use in memory system comprising a memory controller, and a plurality of memory devices inclusive of the memory device connected to the controller via a common bus with a multi-drop connection, the memory device comprising:
- a register containing a device identifier;
- a device identifier comparator that compares selected bits of a received input address to contents of the register to determine if there is a match, and wherein the memory device is selected if the device identifier comparator determines there is a match;
- a burst data controller that causes the memory device to be selected:
- when the device identifier comparator determines there is a match;
- while a command input is in progress;
- and
- while an address input is in progress.
A memory device for use in memory system comprising a memory controller, and a plurality of memory devices inclusive of the memory device connected to the controller via a common bus with a multi-drop connection, the memory device comprising:
- a register containing a device identifier;
- a device identifier comparator that compares selected bits of a received input address to contents of the register to determine if there is a match, and wherein the memory device is selected if the device identifier comparator determines there is a match;
- wherein the memory device further comprises:
- a write enable buffer for buffering a received write enable signal, the write buffer having an input for receiving an indication of whether that memory device is selected or deselected, and wherein the write enable buffer is disabled when the memory device is deselected;
- a read enable buffer for buffering a received read enable signal, the read buffer having an input for receiving an indication of whether that memory device is selected or deselected, and wherein the read enable buffer is disabled when the memory device is deselected.
A memory device for use in memory system comprising a memory controller, and a plurality of memory devices inclusive of the memory device connected to the controller via a common bus with a multi-drop connection, the memory device comprising:
- a register containing a device identifier;
- a device identifier comparator that compares selected bits of a received input address to contents of the register to determine if there is a match, and wherein the memory device is selected if the device identifier comparator determines there is a match;
- wherein the common bus comprises:
- a write protect line;
- a write enable line;
- a read enable line;
- an address latch enable line;
- a command latch enable line;
- a chip enable line;
- an I/O for command, address and data;
- and
- a ready/busy line.
A method for use in a memory system comprising a memory controller and a plurality of memory devices connected to the controller via a common bus with a multi-drop connection, the method comprising:
- the memory controller performing device selection by input address;
- each memory device maintaining a device identifier in a register;
- a device identifier comparator in each memory device comparing selected bits of a received input address to contents of the register of the memory device to determine if there is a match, and wherein a given device is selected if the device identifier comparator of the given device determines there is a match;
- a burst data controller in each memory device causing the memory device to be selected:
- when the device identifier comparator determines there is a match;
- while a command input is in progress;
- and
- while an address input is in progress.
A method for use in a memory system comprising a memory controller and a plurality of memory devices connected to the controller via a common bus with a multi-drop connection, the method comprising:
- the memory controller performing device selection by input address;
- each memory device maintaining a device identifier in a register;
- a device identifier comparator in each memory device comparing selected bits of a received input address to contents of the register of the memory device to determine if there is a match, and wherein a given device is selected if the device identifier comparator of the given device determines there is a match;
- the method further comprising, in each memory device:
- buffering a received write enable signal in a write buffer, the write buffer having an input for receiving an indication of whether that memory device is selected or deselected, and wherein the write enable buffer is disabled when the memory device is deselected;
- for buffering a received read enable signal in a read buffer, the read buffer having an input for receiving an indication of whether that memory device is selected or deselected, and wherein the read enable buffer is disabled when the memory device is deselected.
A method for use in a memory system comprising a memory controller and a plurality of memory devices connected to the controller via a common bus with a multi-drop connection, the method comprising:
- the memory controller performing device selection by input address;
- each memory device maintaining a device identifier in a register;
- a device identifier comparator in each memory device comparing selected bits of a received input address to contents of the register of the memory device to determine if there is a match, and wherein a given device is selected if the device identifier comparator of the given device determines there is a match;
- the method further comprising using a common bus comprising:
- a write protect line;
- a write enable line;
- a read enable line;
- an address latch enable line;
- a command latch enable line;
- a chip enable line;
- an I/O for command, address and data;
- and
- a ready/busy line.
Dependencies are inferred from the claim text.