Thyristor memory and methods of operation
AssigneeMicron Technology, Inc.
InventorRajesh N. Gupta
Life of this patent
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Abstract
Apparatuses and methods can include write schemes for a thyristor memory cell in which an access pulse applied to the gate of the thyristor memory cell is adjusted relative to the data pulse to write data into the thyristor memory cell. Some of the write schemes may substantially reduce or eliminate an unselected data line disturb. In various embodiments, the thyristor memory cell can be structured with two control nodes and its cathode or anode coupled to a reference voltage node common to all thyristor memory cells in a memory array. Additional apparatuses and methods are disclosed.
Claims13
A method of writing data to a thyristor memory cell, comprising:
- applying a data pulse to a data line coupled to a first end of the thyristor memory cell, the thyristor memory cell having a second end coupled to a fixed voltage;
- and
- applying an access pulse to an access line coupled to a gate of the thyristor memory cell, the access pulse and the data pulse structured such that, after writing to the thyristor memory cell, a base of the thyristor memory cell is programmed to a voltage such that the thyristor memory cell is undisturbed by reading another thyristor memory cell coupled to the data line, wherein the access pulse is further structured such that the base is programmed to a voltage below a level where the thyristor memory cell latches without assist of a pulse applied to the gate of the thyristor memory cell.
An apparatus comprising:
- a thyristor memory cell having a first end, a gate, and a second end, the first end coupled to a data line, the gate coupled to an access line, the second end coupled to a reference node;
- and
- control circuitry coupled to the data line and coupled to the access line, the control circuitry configured to apply a data pulse to the data line and an access pulse to the access line, the access pulse and the data pulse structured such that, after writing to the thyristor memory cells, a base of the thyristor memory cell is programmed to a voltage such that the thyristor memory cell is undisturbed by reading another thyristor memory cell coupled to the data line, wherein the access pulse is further structured such that the base is programmed to a voltage below a level where the thyristor memory cell latches without assist of a pulse applied to the gate of the thyristor memory cell.
Dependencies are inferred from the claim text.