Memory elements with soft error upset immunity

A memory element comprising:

• at least five transistor pairs interconnected to form a bistable cell, wherein each of the five transistor pairs forms an inverter-type circuit that generates an output from at least two logically equivalent inputs, wherein the two logically equivalent inputs for three of the five transistor pairs are logic ones, and wherein the two logically equivalent inputs for two of the five transistor pairs are logic zeros.

A memory element comprising:

• at least ten transistors interconnected to form a bistable cell that stores a data signal, wherein the at least ten transistors are together operable to store the data signal;
• and
• at least a pair of address transistors through which the data signal is loaded into the bistable cell, wherein each of the ten transistors has a gate terminal that receives an input, wherein the bistable cell has first and second data storage nodes that are logically equivalent and first, second, and third complementary data storage nodes that are logically equivalent, and wherein four of the transistors interconnected to form the bistable cell are connected together in series between a positive power supply line and a ground power supply line.

A memory element comprising:

• at least ten transistors interconnected to form a bistable cell that stores a data signal, wherein the at least ten transistors are together operable to store the data signal;
• and
• at least a pair of address transistors through which the data signal is loaded into the bistable cell, wherein each of the ten transistors has a gate terminal that receives an input, wherein the bistable cell has first and second data storage nodes that are logically equivalent and first, second, and third complementary data storage nodes that are logically equivalent, wherein the inputs of three of the ten transistors are connected to the first data storage node, wherein the inputs of three of the ten transistors are connected to the second data storage node, wherein the inputs of two of the ten transistors are connected to the first complementary data storage node, wherein the input of one of the ten transistors is connected to the second complementary data storage node, and wherein the input of one of the ten transistors is connected to the third complementary data storage node.

A memory element comprising:

• at least first, second, third, and fourth inverter-type circuits that collectively form a bistable cell, wherein at least the first inverter-type circuit comprises at least three transistors connected together in series and wherein each of the at least three transistors receives a distinct logic signal input;
• and
• fifth and sixth inverter-type circuits that together with the first, second, third, and fourth inverter-type circuits form the bistable cell.