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US 8,797,788 B2Granted
Semiconductor device
AssigneeSemiconductor Energy Laboratory Co., Ltd.
InventorYusuke Sekine
Life of this patent
Estimating the term…
Abstract
A nonvolatile memory is provided. A semiconductor device (a nonvolatile memory) has a circuit configuration similar to that of a general SRAM. By providing a transistor whose off-state current is small between a stored data holding portion and a power supply line of the SRAM, leakage of electric charge from the stored data holding portion is prevented. As the transistor whose off-state current is small provided for preventing leakage of electric charge from the stored data holding portion, a transistor including an oxide semiconductor film is preferably used. Such a configuration can also be applied to a shift register, whereby a shift register with low power consumption can be obtained.
Claims10
A semiconductor device comprising a first memory comprising:
- a first transistor, a second transistor, and a third transistor electrically connected to each other in series in order;
- and
- a fourth transistor, a fifth transistor, and a sixth transistor electrically connected to each other in series in order,
- wherein one of a source and a drain of the first transistor and one of a source and a drain of the fourth transistor are electrically connected to a high power supply potential line,
- wherein one of a source and a drain of the third transistor and one of a source and a drain of the sixth transistor are electrically connected to a low power supply potential line,
- wherein a gate of the first transistor and a gate of the third transistor are electrically connected to a third terminal,
- wherein the third terminal is electrically connected between the fifth transistor and the sixth transistor,
- wherein a gate of the fourth transistor and a gate of the sixth transistor are electrically connected to a second terminal,
- wherein the second terminal is electrically connected between the second transistor and the third transistor,
- wherein a gate of the second transistor and a gate of the fifth transistor are electrically connected to a first terminal,
- wherein each of the first transistor and the fourth transistor is a p-channel transistor, and
- wherein each of the second transistor, the third transistor, the fifth transistor, and the sixth transistor is a transistor comprising an oxide semiconductor layer.
9 more elements
A semiconductor device comprising a first memory comprising:
- a first transistor, a second transistor, and a third transistor electrically connected to each other in series in order;
- and
- a fourth transistor, a fifth transistor, and a sixth transistor electrically connected to each other in series in order,
- wherein one of a source and a drain of the first transistor and one of a source and a drain of the fourth transistor are electrically connected to a high power supply potential line,
- wherein one of a source and a drain of the third transistor and one of a source and a drain of the sixth transistor are electrically connected to a low power supply potential line,
- wherein a gate of the first transistor and a gate of the third transistor are electrically connected to a third terminal,
- wherein the third terminal is electrically connected between the fifth transistor and the sixth transistor,
- wherein a gate of the fourth transistor and a gate of the sixth transistor are electrically connected to a second terminal,
- wherein the second terminal is electrically connected between the second transistor and the third transistor,
- wherein a gate of the second transistor and a gate of the fifth transistor are electrically connected to a first terminal,
- wherein each of the first transistor and the fourth transistor is a p-channel transistor,
- wherein each of the second transistor, the third transistor, the fifth transistor, and the sixth transistor is a transistor comprising an oxide semiconductor layer, and
- wherein the semiconductor device is a liquid crystal display device.
10 more elements
A semiconductor device comprising a first memory comprising:
- a first transistor, a second transistor, and a third transistor electrically connected to each other in series in order;
- and
- a fourth transistor, a fifth transistor, and a sixth transistor electrically connected to each other in series in order,
- wherein one of a source and a drain of the first transistor and one of a source and a drain of the fourth transistor are electrically connected to a high power supply potential line,
- wherein one of a source and a drain of the third transistor and one of a source and a drain of the sixth transistor are electrically connected to a low power supply potential line,
- wherein a gate of the first transistor and a gate of the third transistor are electrically connected to a third terminal,
- wherein the third terminal is electrically connected between the fifth transistor and the sixth transistor,
- wherein a gate of the fourth transistor and a gate of the sixth transistor are electrically connected to a second terminal,
- wherein the second terminal is electrically connected between the second transistor and the third transistor,
- wherein a gate of the second transistor and a gate of the fifth transistor are electrically connected to a first terminal,
- wherein each of the first transistor and the fourth transistor is a p-channel transistor,
- wherein each of the second transistor, the third transistor, the fifth transistor, and the sixth transistor is a transistor comprising an oxide semiconductor layer, and
- wherein the oxide semiconductor layer comprises indium and zinc.
10 more elements
Dependencies are inferred from the claim text.