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US 8,797,787 B2Granted
Semiconductor manufacturing method
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorJhon Jhy Liaw
Life of this patent
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Abstract
A memory bit cell includes a latch, a write port coupled to the latch, and a read port coupled to the latch. The write port includes a first set of devices having a first threshold voltage and a second set of devices having a second threshold voltage that is greater than the first threshold voltage. The read port includes a third set of devices having a third threshold voltage that is less than the first threshold voltage.
Claims17
A memory bit cell, comprising:
- a latch;
- a write port coupled to the latch, including a first set of devices having a first threshold voltage, and a second set of devices having a second threshold voltage that is greater than the first threshold voltage;
- and
- a read port coupled to the latch, including a third set of devices having a third threshold voltage that is less than the first threshold voltage,
- wherein the first set of devices are formed in a first well of a first type, the second set of devices are formed in a second well of the first type, and the third set of devices are formed in a third well of the first type, and a fourth set of devices are formed in a first well of a second type.
2 more elements
A method of fabricating a semiconductor memory, comprising:
- forming a first set of devices of a memory bit cell in a semiconductor substrate, the first set of devices having a first threshold voltage;
- forming a second set of devices of the memory bit cell in the semiconductor substrate, the second set of devices having a second threshold voltage that is greater than the first threshold voltage;
- forming a third set of devices of the memory bit cell in the semiconductor substrate, the third set of devices having a third threshold voltage that is less than the first threshold voltage;
- and
- forming a fourth set of devices of the memory bit cell in the semiconductor substrate, the fourth set of devices having a fourth threshold voltage,
- wherein
- forming the first set of devices includes doping the semiconductor substrate to create a first well of a first type,
- forming the second set of devices includes doping the semiconductor substrate to create a second well of the first type,
- forming the third set of devices includes doping the semiconductor substrate to create a third well of the first type, and
- forming the fourth set of devices includes doping the semiconductor substrate to create a first well of a second type.
7 more elements
A semiconductor memory, comprising:
- a plurality of bit cells arranged in a plurality of rows and columns, each of the plurality of rows associated with at least one word line, and each of the plurality of columns associated with at least one bit line,
- wherein a first bit cell is disposed in a first row and a first column and includes:
- a write port including a first set of devices having a first threshold voltage, and a second set of devices having a second threshold voltage that is greater than the first threshold voltage;
- and
- a read port including a third set of devices having a third threshold voltage that is less than the first threshold voltage,
- wherein the first set of devices are formed in a first well of a first type, the second set of devices are formed in a second well of the first type, the third set of devices are formed in a third well of the first type, and a fourth set of devices are formed in a first well of a second type.
3 more elements
Dependencies are inferred from the claim text.