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US 8,797,780 B2Granted
Memory device having sub-bit lines and memory system
AssigneeSamsung Electronics Co., Ltd.
InventorsDoo Sub Lee, Pan Suk Kwak
Life of this patent
Estimating the term…
Abstract
A memory device includes; a memory cell array including a memory cell connected to a bit line, a page buffer unit receiving data from the memory cell via the bit line, and a contact unit providing an electrical path through which the data is communicated from the memory cell array to the page buffer unit, wherein the contact unit comprises a sub-bit line configured to connect the bit line via a first contact with the page buffer unit via a second contact.
Claims18
A memory device comprising:
- a memory cell array comprising a memory cell connected to a bit line;
- a contact region into which the bit line extends horizontally and comprising a first portion of a sub-bit line which is vertically displaced relative to the bit line, wherein the bit line is connected to the sub-bit line via a first contact extending vertically between the bit line and the sub-bit line;
- and
- a page buffer region comprising a second portion of the sub-bit line connected to a second contact,
- wherein the contact region is located between the memory cell array and the page buffer region,
- wherein the first contact is formed in the contact region and the second contact is formed in the page buffer region,
- wherein the second contact has a greater width than the first contact.
4 more elements
A memory device comprising:
- a memory cell array comprising a memory cell connected to a bit line;
- a contact region comprising a first portion of a sub-bit line connected to the bit line via a first contact;
- and
- a page buffer region comprising a second portion of the sub-bit line connected to a second contact,
- wherein the contact region is located between the memory cell array and the page buffer region,
- wherein the first contact is formed in the contact region and the second contact is formed in the page buffer region,
- wherein the second contact has a greater width than the first contact, and
- wherein the sub-bit line has a greater width than the bit line.
5 more elements
A memory device comprising:
- a memory cell array comprising a memory cell connected to a bit line;
- a contact region comprising a first portion of a sub-bit line connected to the bit line via a first contact;
- and
- a page buffer region comprising a second portion of the sub-bit line connected to a second contact,
- wherein the contact region is located between the memory cell array and the page buffer region,
- wherein the first contact is formed in the contact region and the second contact is formed in the page buffer region,
- wherein the second contact has a greater width than the first contact, and
- wherein a region of a substrate below the contact region is devoid of a transistor.
5 more elements
A memory device comprising:
- a memory cell array comprising a memory cell connected to a bit line;
- a contact region comprising a first portion of a sub-bit line connected to the bit line via a first contact;
- and
- a page buffer region comprising a second portion of the sub-bit line connected to a second contact,
- wherein the contact region is located between the memory cell array and the page buffer region,
- wherein the first contact is formed in the contact region and the second contact is formed in the page buffer region,
- wherein the second contact has a greater width than the first contact, and
- wherein a region of a substrate below the contact region is devoid of a gate structure.
5 more elements
A memory device comprising:
- a memory cell array comprising a memory cell connected to a bit line;
- a contact region comprising a first portion of a sub-bit line connected to the bit line via a first contact;
- and
- a page buffer region comprising a second portion of the sub-bit line connected to a second contact,
- wherein the contact region is located between the memory cell array and the page buffer region,
- wherein the first contact is formed in the contact region and the second contact is formed in the page buffer region,
- wherein the second contact has a greater width than the first contact, and
- wherein the contact region is devoid of a gate structure.
5 more elements
A memory device comprising:
- a memory cell array comprising a memory cell connected to a bit line;
- a contact region comprising a first portion of a sub-bit line connected to the bit line via a first contact;
- and
- a page buffer region comprising a second portion of the sub-bit line connected to a second contact,
- wherein the contact region is located between the memory cell array and the page buffer region,
- wherein the first contact is formed in the contact region and the second contact is formed in the page buffer region,
- wherein the second contact has a greater width than the first contact,
- wherein the sub-bit line has a greater width than the bit line,
- wherein a region of a substrate below the contact region is devoid of a transistor.
6 more elements
A solid state drive (SSD) including a memory device, wherein the memory device comprises:
- a memory cell array comprising a memory cell connected to a bit line;
- a contact region into which the bit line extends horizontally and comprising a first portion of a sub-bit line which is vertically displaced relative to the bit line, wherein the bit line is connected to the sub-bit line bit line via a first contact extending vertically between the bit line and the sub-bit line;
- and
- a page buffer region comprising a second portion of the sub-bit line connected to a second contact,
- wherein the contact region is located between the memory cell array and the page buffer region,
- wherein the first contact is formed in the contact region and the second contact is formed in the page buffer region,
- wherein the second contact has a greater width than the first contact.
4 more elements
Dependencies are inferred from the claim text.