Memory module with memory stack and interface with enhanced capabilites

A method comprising:

• communicating with a memory stack and a memory controller, wherein the memory stack includes a first physical memory device and a second physical memory device, and wherein each of the first physical memory device and the second physical memory device includes a respective plurality of physical memory banks;
• simulating a virtual memory device having a first virtual memory bank and a second virtual memory bank, the first virtual memory bank simulated using at least a particular physical memory bank of the first physical memory device, and the second virtual memory bank simulated using at least a particular physical memory bank of the second physical memory device;
• presenting the virtual memory device to the memory controller;
• and
• performing a per-pin timing calibration to compensate for timing variations between signals received from the first physical memory device and signals received from the second physical memory device.

An apparatus comprising:

• a host system comprising a memory controller;
• and
• a dual in-line memory module (DIMM) comprising:
• a memory stack comprising a first physical dynamic random access memory (DRAM) integrated circuit and a second physical DRAM integrated circuit, wherein each of the first physical DRAM integrated circuit and the second physical DRAM integrated circuit comprises a respective plurality of physical memory banks;
• and
• a buffer circuit coupled to the memory controller, the buffer circuit configured to:
• communicate with the memory stack and the memory controller;
• simulate a virtual DRAM integrated circuit having a first virtual memory bank and a second virtual memory bank, the first virtual memory bank simulated using at least a particular physical memory bank of the first physical DRAM integrated circuit, and the second virtual memory bank simulated using at least a particular physical memory bank of the second physical DRAM integrated circuit;
• present the virtual DRAM integrated circuit to the memory controller;
• and
• perform a per-pin timing calibration to compensate for timing variations between signals received from the first physical DRAM integrated circuit and signals received from the second physical DRAM integrated circuit.