US 8,797,778 B2 · Semiconductor memory device having open bit line structure

Abstract

A semiconductor memory device has an array structure of an open bit line structure and comprises a plurality of normal memory mats, two dummy mats and a plurality of rows of sense amplifiers. The normal memory mat includes a plurality of memory cells and arranged in a bit line extending direction, while the dummy mat includes a plurality of dummy cells and arranged in a bit line extending direction at both ends of the plurality of normal memory mats. The rows of sense amplifiers are arranged between the normal memory mats and between each of the normal memory mats and each of the dummy mats. A first predetermined number of the dummy cells, the number of which is smaller than a number of the memory cells arranged along each bit line of the normal memory mats, are arranged along each bit line of the dummy mats.

Claims16

Dependent claims

A semiconductor device comprising:

a plurality of sense amplifiers each including first and second sense nodes;
a plurality of first lines each connected to the first sense node of an associated one of the sense amplifiers;
a plurality of second lines;
a plurality of resistive elements each connected in series between an associated one of the second lines and the second sense node of an associated one of the sense amplifiers;
a plurality of third lines intersecting the first lines;
a plurality of first memory cells each disposed at an associated one of intersections of the first lines and the third lines;
at least one fourth line intersecting the second lines;
and
a plurality of second memory cells each disposed at an associated one of intersections of the second lines and the fourth line.

6 more elements

A semiconductor device comprising:

a plurality of memory arrays arranged in line in a first direction, the memory arrays thereby including a first end memory array, a second end memory array and at least one intermediate memory array between the first and second end memory arrays;
and
a plurality of sense amplifier sets, each of the sense amplifier sets being between associated adjacent ones of the memory arrays and including a plurality of sense amplifiers arranged in line in a second direction crossing the first direction;
the at least one intermediate memory array including:
a plurality of first bit lines each extending in the first direction and belonging to one of the sense amplifier sets,
a plurality of second bit lines each extending in the first direction and belonging to a different one of the sense amplifier sets,
a plurality of first word lines each extending in the second direction to cross the first and second bit lines, and
a plurality of first memory cells each disposed at an associated one of crossing points of the first word lines and the first and second bit lines;
each of the first and second end memory arrays including:
a plurality of third bit lines each extending in the first direction and belonging to one of the sense amplifier sets,
a plurality of fourth bit lines each extending in the first direction and connected to no one of the sense amplifier sets,
a plurality of second word lines each extending in the second direction to cross the third and fourth bit lines, the second word lines being smaller in number than the first word lines, and
a plurality of second memory cells each disposed at an associated one of crossing points of the second word lines and the third and fourth bit lines, the second memory cells being smaller in number than the first memory cells of the at least one of the intermediate memory array.

10 more elements

A semiconductor device comprising:

a plurality of memory arrays arranged in line in a first direction, the memory arrays thereby including a first end memory array, a second end memory array and at least one intermediate memory array between the first and second end memory arrays;
a plurality of first sense amplifiers disposed between the first end memory array and the at least one intermediate memory array and arranged in line in a second direction crossing the first direction, each of the first sense amplifiers including first and second sense nodes and amplifying, when activated, a potential between the first and second sense nodes;
and
a plurality of second sense amplifiers disposed between the second end memory array and an intermediate memory array of the at least one intermediate memory array and arranged in line in the second direction, each of the second sense amplifiers including third and fourth sense nodes and amplifying, when activated, a potential between the third and fourth sense nodes;
the first end memory array including:
a plurality of first bit lines each extending in the first direction and each operatively connected to the first sense node of an associated one of the first sense amplifiers,
a plurality of second bit lines each extending in the first direction and connected to no one of the first sense amplifiers, and
a plurality of first memory cell sets, each of the first memory cell sets including a plurality of memory cells and being connected to an associated one of the first bit lines;
the at least one intermediate memory array including:
a plurality of third bit lines each extending in the first direction and each operatively connected to the second sense node of an associated one of the first sense amplifiers, each of the third bit lines being larger in length than each of the first bit lines, and
a plurality of second memory cell sets, each of the second memory cell sets including a plurality of memory cells and being connected to an associated one of the third bit lines, each of the second memory cell sets being larger in number of memory cells than each of the first memory cell sets;
and
the second end memory array including:
a plurality of fourth bit lines each extending in the first direction and each operatively connected to the third sense node of an associated one of the second sense amplifiers,
a plurality of fifth bit lines each extending in the first direction and connected to no one of the second sense amplifiers, and
a plurality of third memory cell sets, each of the third memory cell sets including a plurality of memory cells and being connected to an associated one of the fourth bit lines.

13 more elements

Dependencies are inferred from the claim text.

Semiconductor memory device having open bit line structure

Life of this patent

Semiconductor memory device having open bit line structure

Life of this patent

Abstract

Claims16