Semiconductor memory device
AssigneeKabushiki Kaisha Toshiba
InventorsTomoo Hishida, Yoshihisa Iwata
Life of this patent
Estimating the term…
Abstract
A semiconductor memory device comprises: a semiconductor substrate; a plurality of memory units provided on the semiconductor substrate and each including a plurality of memory cells that are stacked; and a plurality of bit lines formed above each of a plurality of the memory units aligned in a column direction, an alignment pitch in a row direction of the plurality of bit lines being less than an alignment pitch in the row direction of the memory units, and an end of each of the memory units aligned in the column direction being connected to one of the plurality of bit lines formed above the plurality of the memory units aligned in the column direction.
Claims20
A semiconductor memory device, comprising:
- a semiconductor substrate;
- memory units including memory cells that are stacked above the semiconductor substrate, the memory units including a first memory unit, a second memory unit, and a third memory unit, the second memory unit being adjacent to the first memory unit in a first direction, the third memory unit being adjacent to the first memory unit in a second direction perpendicular to the first direction;
- and
- bit lines disposed above the memory units, the bit lines extending in the second direction, the bit lines including a first bit line and a second bit line, the second bit line being adjacent to the first bit line in the first direction, wherein
- a first pitch is larger than a second pitch, the first pitch being a distance between the first memory unit and the second memory unit, the second pitch being a distance between the first bit line and the second bit line.
A semiconductor memory device, comprising:
- a semiconductor substrate;
- memory units including memory cells that are stacked above the semiconductor substrate, the memory units being arranged with a first pitch in a row direction;
- bit lines disposed above the memory units with a second pitch in the row direction, the bit lines extending in a column direction, the column direction being perpendicular to the row direction, the first pitch is larger than the second pitch;
- and
- a bit line contact connected to one of the memory units,
- the bit line contact being connected to one of the bit lines.
A semiconductor memory device, comprising:
- a semiconductor substrate;
- memory units including memory cells that are stacked above the semiconductor substrate, the memory units including a first memory unit, a second memory unit, and a third memory unit, the second memory unit being adjacent to the first memory unit in a first direction, the third memory unit being adjacent to the first memory unit in a second direction perpendicular to the first direction;
- and
- bit lines disposed above the memory units, the bit lines extending in the second direction, the bit lines including a first bit line and a second bit line, the second bit line being adjacent to the first bit line in the first direction, wherein
- a number of the memory cells that are simultaneously written or read is greater than a number of the memory units aligned in the first direction.
Dependencies are inferred from the claim text.