Parallel test payload

#The present disclosure relates generally to parallel test payloads.

#Digital information is often encoded in analog carriers on data-bearing media, such as magnetic oxide particles (e.g., on a magnetic strip), electromagnetic signals, optically readable symbols created by physical etchings (e.g., on a digital video disk (DVD)), or ink (e.g., on paper). The rate of correct recovery for digital information encoded in analog carriers is variable and depends upon a variety of factors. For example, small variations in individual implementation for a given class of systems with a particular analog carrier can alter the recovery rate.

#Features and advantages of examples of embodiments of the present disclosure will become apparent by reference to the following detailed description and drawings, in which like reference numerals correspond to similar, though perhaps not identical, components. For the sake of brevity, reference numerals or features having a previously described function may or may not be described in connection with other drawings in which they appear.

#FIG. 1 is a schematic diagram depicting an example of a system for performing an example of a parallel calibration method;

#FIG. 2 is an example of a parallel test payload;

#Embodiments of the test payload disclosed herein include codes that are uniformly represented in each variable bit length. Such payloads may be used to test an analog carrier for all bit length codes in parallel. As such, the test payload described herein circumvents the need to perform separate procedures for each possible bit length in order to uniformly measure all possible codes. Furthermore, the system disclosed herein compares all possible codes in a multi-bit encoding population simultaneously (and with equal frequency). The payload blocks (i.e., the various sub-sequences) have variable bit densities but are all tested together. Using the single test payload disclosed herein enables relatively simple parallel calibration and implementation of systems with variable bit length codes.

#An embodiment of a system 100 for performing an embodiment of a parallel calibration method is illustrated in FIG. 1. Very generally, the system 100 includes various sub-systems and/or components (each of which will be described further herein) configured for performing one or more of the method steps. The overall system 100 may include a network of interconnected computers and/or other electronic devices (e.g., scanners, printers, etc.), including virtualized and/or redundant processors, banks of processors and/or servers, etc. It is to be understood that the components of the system 100 may be implemented in a consolidated location, or portion(s) of the system 100 may be implemented at different locations.

#The hardware of at least some of the sub-systems includes an electronic processing device, such as, for example, a controller, a micro controller, a microprocessor, a host processor, an application specific integrated circuit (ASIC), and/or a reprogrammable hardware logic device (such as a field programmable gate array (FPGA)). It is to be understood that the electronic processing device may be a processor working in conjunction with a central processing unit (CPU) performing the function of a general-purpose processor. Computer program(s) and/or software (e.g., computer readable code) may be loaded onto one or more of the sub-systems, and stored in a memory thereof. Such programs and/or software are executable via a processing device.