Poly-phase filter, and a single-side band mixer including the same
AssigneeFujitsu Limited
InventorKazuaki Oishi
Life of this patent
Estimating the term…
Abstract
A 4-phase filter includes four filter units including resistors and capacitors which inputs input signals, and provides the input signal via a switch buffer to a secondary capacitor provided in parallel to a primary capacitance of each filter unit, thus enabling a shift of an operational frequency band according to whether or not the switch buffer is in an output-high-impedance state.
Claims13
A poly-phase filter inputting an input signal and outputting first-fourth 4-phase output signals, comprising:
- first-fourth resistors, each of which has an input terminal and an output terminal;
- a first primary capacitor provided between the output terminal of the first resistor and the input terminal of the fourth resistor;
- a second primary capacitor provided between the output terminal of the second resistor and the input terminal of the first resistor;
- a third primary capacitor provided between the output terminal of the third resistor and the input terminal of the second resistor;
- a fourth primary capacitor provided between the output terminal of the fourth resistor and the input terminal of the third resistor;
- an input buffer which inputs and outputs to the input terminals of the first-fourth resistors the input signal;
- a first secondary capacitor which is connected to the output terminal of the first resistor in parallel to the first primary capacitor;
- a first switch buffer which inputs and outputs to the first secondary capacitor the input signal being input to the input terminal of the fourth resistor;
- a second secondary capacitor which is connected to the output terminal of the second resistor in parallel to the second primary capacitor;
- a second switch buffer which inputs and outputs to the second secondary capacitor the input signal being input to the input terminal of the first resistor;
- a third secondary capacitor which is connected to the output terminal of the third resistor in parallel to the third primary capacitor;
- a third switch buffer which inputs and outputs to the third secondary capacitor the input signal being input to the input terminal of the second resistor;
- a fourth secondary capacitor which is connected to the output terminal of the fourth resistor in parallel to the fourth primary capacitor;
- and
- a fourth switch buffer which inputs and outputs to the fourth secondary capacitor the input signal being input to the input terminal of the third resistor, wherein
- the first-fourth output signals are respectively output from the output terminals of the first-fourth resistors, and
- the first-fourth switch buffers are controlled, in response to a switching signal, to be either output-high-impedance state or not.
A poly-phase filter inputting an input signal and outputs 4-phase first-fourth output signals, comprising:
- a first-stage filter unit circuit which inputs the input signal and outputs the 4-phase signals;
- and
- a second-stage filter unit circuit which inputs the 4-phase signal output from the first-stage filter unit circuit,
- wherein each of the first- and the second-stage filter unit circuits comprises:
- first-fourth resistors each of which has an input terminal and an output terminal;
- a first primary capacitor provided between the output terminal of the first resistor and the input terminal of the fourth resistor;
- a second primary capacitor provided between the output terminal of the second resistor and the input terminal of the first resistor;
- a third primary capacitor provided between the output terminal of the third resistor and the input terminal of the second resistor;
- and
- a fourth primary capacitor provided between the output terminal of the fourth resistor and the input terminal of the third resistor,
- wherein the first-stage filter unit circuit comprises:
- an input buffer which inputs and outputs to the input terminals of the first-fourth resistors the input signal;
- a first secondary capacitor which is connected to the output terminal of the first resistor in parallel to the first primary capacitor;
- a first switch buffer inputs and outputs to the first secondary capacitor the input signal being input to the input terminal of the fourth resistor;
- a second secondary capacitor which is connected to the output terminal of the second resistor in parallel to the second primary capacitor;
- a second switch buffer which inputs and outputs to the second secondary capacitor the input signal being input to the input terminal of the first resistor;
- a third secondary capacitor which is connected to the output terminal of the third resistor in parallel to the third primary capacitor;
- a third switch buffer which inputs and outputs to the third secondary capacitor the input signal being input to the input terminal of the second resistor;
- a fourth secondary capacitor which is connected to the output terminal of the fourth resistor in parallel to the fourth primary capacitor;
- and
- a fourth switch buffer which inputs and outputs to the fourth secondary capacitor the input signal being input to the input terminal of the third resistor,
- wherein the first-fourth output signals are respectively output from the output terminals of the first-fourth resistors of the second-stage filter unit circuit, and
- the first-fourth switch buffers are controlled, in response to a switching signal, to be either output high-impedance state or not.
A poly-phase filter inputting first and second input signals, of which phases are shifted from each other, and outputting first-fourth 4-phase output signals, comprising:
- first-fourth resistors, each of which includes an input terminal and an output terminal;
- a first primary capacitor provided between the output terminal of the first resistor and the input terminal of the fourth resistor;
- a second primary capacitor provided between the output terminal of the second resistor and the input terminal of the first resistor;
- a third primary capacitor provided between the output terminal of the third resistor and the input terminal of the second resistor;
- a fourth primary capacitor provided between the output terminal of the fourth resistor and the input terminal of the third resistor;
- a first input buffer which inputs and outputs to the input terminals of the first and second resistors the first input signal;
- a second input buffer which inputs and outputs to the input terminals of the third and fourth resistors the second input signal;
- a first secondary capacitor which is connected to the output terminal of the first resistor in parallel to the first primary capacitor;
- a first switch buffer which inputs and outputs to the first secondary capacitor the second input signal;
- a second secondary capacitor which is connected to the output terminal of the second resistor in parallel to the second primary capacitor;
- a second switch buffer which inputs and outputs to the second secondary capacitor the first input signal;
- a third secondary capacitor which is connected to the output terminal of the third resistor in parallel to the third primary capacitor;
- a third switch buffer which inputs and outputs to the third secondary capacitor the first input signal;
- a fourth secondary capacitor which is connected to the output terminal of the fourth resistor in parallel to the fourth primary capacitor;
- and
- a fourth switch buffer which inputs and outputs to the fourth secondary capacitor the second input signal, wherein
- the first-fourth output signals are respectively output from the output terminals of the first-fourth resistors, and
- the first-fourth switch buffers are controlled, in response to a switching signal, to be either output high-impedance state or not.
A poly-phase filter inputting first-fourth input signals, of which phases are shifted from one another, and outputting first-fourth 4-phase output signals, comprising:
- first-fourth resistors, each of which has an input terminal and an output terminal;
- a first primary capacitor provided between the output terminal of the first resistor and the input terminal of the fourth resistor;
- a second primary capacitor provided between the output terminal of the second resistor and the input terminal of the first resistor;
- a third primary capacitor provided between the output terminal of the third resistor and the input terminal of the second resistor;
- a fourth primary capacitor provided between the output terminal of the fourth resistor and the input terminal of the third resistor;
- first-fourth input buffers which respectively input and output to the input terminals of the first-fourth resistors the first-fourth input signals;
- a first secondary capacitor which is connected to the output terminal of the first resistor in parallel to the first primary capacitor;
- a first switch buffer which inputs and outputs to the first secondary capacitor the fourth input signal;
- a second secondary capacitor which is connected to the output terminal of the second resistor in parallel to the second primary capacitor;
- a second switch buffer which inputs and outputs to the second secondary capacitor the first input signal;
- a third secondary capacitor which is connected to the output terminal of the third resistor in parallel to the third primary capacitor;
- a third switch buffer which inputs and outputs to the third secondary capacitor the second input signal;
- a fourth secondary capacitor which is connected to the output terminal of the fourth resistor in parallel to the fourth primary capacitor;
- and
- a fourth switch buffer which inputs and outputs to the fourth secondary capacitor the third input signal, wherein
- the first-fourth output signals are respectively output from the output terminals of the first-fourth resistors, and
- the first-fourth switch buffers are controlled, in response to a switching signal, to be either output-high-impedance state or not.
Dependencies are inferred from the claim text.