Buffer input impedance compensation in a reference clock signal buffer

A system for regulating crystal oscillator (XO) input impedance, the system comprising:

• an XO;
• a signal buffer coupled to the XO and configured to drive a reference clock signal generated by the XO;
• and
• a first integrated circuit (IC) coupled to the signal buffer, the first IC comprising:
• an XO input buffer configured to receive the reference clock signal, wherein the XO input buffer is configured to be in an enabled, operational state or to be in a disabled state, and wherein the XO input buffer has a first operational impedance while in the enabled state;
• and
• impedance compensation means for substantially equalizing an input impedance observed at the signal buffer with the first operational impedance while the XO input buffer is in the disabled state, wherein the impedance compensation means is configured to consume less current in its enabled state than the XO input buffer is configured to consume in its enabled state.

A method of operating a wireless transceiver unit, the method comprising:

• supplying a source reference signal to an input of a first integrated circuit (IC), the first IC comprising an input buffer that presents a first impedance at the input while the input buffer is in an enabled state, the input buffer being configured to be in the enabled state or in a disabled state;
• changing the state of the input buffer from the enabled state to the disabled state and setting a first control signal associated with the input buffer;
• presenting a second impedance at the input while the input buffer is in the disabled state, wherein the second impedance is substantially equivalent to the first impedance and is configured to consume less current than the input buffer is configured to consume in its enabled state;
• and
• enabling an impedance equivalence structure of the first IC and setting a second control signal associated with the impedance equivalence structure wherein the second control signal is obtained by inverting the first control signal.

A non-transitory computer program product residing on a processor-executable computer storage medium, the computer program product comprising processor-executable instructions configured to cause a processor to:

• identify a first integrated circuit (IC), the first IC comprising an input configured to receive a source reference signal and an input buffer that presents a first impedance at the input while the input buffer is in an enabled state, the input buffer being configured to be in the enabled state or in a disabled state;
• change the state of the input buffer from the enabled state to the disabled state and set a first control signal associated with the input buffer;
• configure a second impedance to be presented at the input in response to the input buffer being in the disabled state, wherein the second impedance is substantially equivalent to the first impedance and is configured to consume less current than the input buffer is configured to consume in its enabled state;
• and
• enable an impedance equivalence structure of the first IC and set a second control signal associated with the impedance equivalence structure wherein the second control signal is obtained by inverting the first control signal.