Circuits, apparatuses, and methods for delay models
AssigneeMicron Technology, Inc.
InventorsVenkatraghavan Bringivijayaraghavan, Jason Brown, Tyler J. Gomm
Life of this patent
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Abstract
Circuits, apparatuses, and methods are disclosed for delay models. In one such example circuit, a first delay model circuit is configured to provide a first output signal by modeling a delay of a signal through a path. A second delay model circuit is configured to provide a second output signal by modeling the delay of the signal through the path. A compare circuit is coupled to the first and second delay model circuits. The compare circuit is configured to compare a third signal from the first delay model circuit and a fourth signal from the second delay model circuit, and, in response provide an adjustment signal to adjust the delay of the second delay model circuit.
Claims18
A circuit, comprising:
- a first delay model circuit configured to provide a first output signal by modeling a delay of a signal through a path;
- a second delay model circuit configured to provide a second output signal by modeling the delay of the signal through the path;
- a switch circuit coupled to the first and second delay model circuits and configured to select between the first and second output signals to provide a delayed output signal;
- and
- a compare circuit coupled to the first and second delay model circuits and configured to compare a third signal from the first delay model circuit and a fourth signal from the second delay model circuit, and, in response provide an adjustment signal to adjust the delay of the second delay model circuit.
An apparatus, comprising:
- a compare circuit configured to compare a first delay model and a second delay model and provide an adjustment signal responsive thereto;
- and
- an adjustment circuit coupled to the compare circuit and configured to adjust coarse tune and fine tune the second delay model responsive to the adjustment signal.
A method, comprising:
- providing a first delayed signal by modeling a path in a first delay model circuit;
- providing a second delayed signal by modeling the path in a second delay model circuit;
- providing the first delayed signal as an output signal;
- providing an adjustment signal responsive to comparing the first delayed signal and the second delayed signal;
- adjusting the second delay model circuit to provide an adjusted delayed signal responsive to the adjustment signal;
- and
- switching to provide the adjusted delayed signal as the output signal.
A method, comprising:
- comparing a first signal provided by a first delay model circuit and a second signal provided by a second delay model circuit;
- providing the first signal as an output signal;
- providing an adjustment signal responsive to the comparing;
- adjusting the second delay model circuit responsive to the adjustment signal;
- and
- switching to provide an adjusted output of the second delay model circuit as a clock signal.
A circuit, comprising:
- a first delay model circuit configured to provide a first output signal by modeling a delay of a signal through a path;
- a second delay model circuit configured to provide a second output signal by modeling the delay of the signal through the path, wherein the second delay model circuit is configured to consume less power than the first delay model circuit;
- and
- a compare circuit coupled to the first and second delay model circuits and configured to compare a third signal from the first delay model circuit and a fourth signal from the second delay model circuit, and, in response provide an adjustment signal to adjust the delay of the second delay model circuit.
Dependencies are inferred from the claim text.