Master-slave flip-flop circuit
AssigneeFujitsu Limited
InventorRyuhei Sasagawa
Life of this patent
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Abstract
A master-slave flip-flop circuit includes: a master circuit to receive input data in a first state of a reference clock and hold the input data in a second state of the reference clock to output intermediary data; and a slave circuit to receive the intermediary data in the second state and hold the intermediary data in the first state to output data, wherein the master circuit includes: a feedback two-input NOR gate to receive an output of the master circuit and a first clock; an input three-input NOR gate to receive the input data, a second clock, and a third clock; and a synthesis two-input NOR gate to receive an output of the input three-input NOR gate and an output of the feedback two-input NOR gate.
Claims8
A master-slave flip-flop circuit comprising:
- a master circuit configured to receive input data in a first state of a reference clock and hold the input data in a second state of the reference clock to output intermediary data;
- and
- a slave circuit configured to receive the intermediary data in the second state of the reference clock and hold the intermediary data in the first state of the reference clock to output data,
- wherein the master circuit includes:
- a feedback two-input NOR gate configured to receive an output of the master circuit and a first clock obtained by delaying the reference clock by a first delay amount that is less than a second delay amount and then inverted;
- an input three-input NOR gate configured to receive the input data, a second clock obtained by delaying the reference clock by the second delay amount, and a third clock obtained by delaying the reference clock by a third delay amount that is greater than the second delay amount;
- and
- a synthesis two-input NOR gate configured to receive an output of the input three-input NOR gate and an output of the feedback two-input NOR gate.
Dependencies are inferred from the claim text.