Duty ratio correction circuit, double-edged device, and method of correcting duty ratio

A double-edged device, comprising:

• a duty ratio correction circuit;
• and
• a double-edged circuit, wherein
• the duty ratio correction circuit includes:
• a frequency divider configured to output a second clock signal having a first level that is inverted at a timing of a first edge of a first clock signal and a third clock signal having a second level that is inverted at a timing of a second edge of the first clock signal;
• phase interpolator configured to generate a fourth clock signal and a fifth clock signal by phase interpolation of the second clock signal, the third clock signal, a first inverted signal that is obtained by inverting the second clock signal, or an second inverted signal that is obtained by inverting the third clock signal;
• and
• a multiplier configured to output an exclusive OR signal of the fourth clock signal and the fifth clock signal as a sixth clock signal, and
• the double-edged circuit operates in synchronization with the timing of one of the first edge and the second edge of the sixth clock signal.

A method of correcting a duty ratio, comprising:

• outputting a second clock signal having a first level that is inverted at a timing of a first edge of a first clock signal;
• outputting a third clock signal having a second level that is inverted at a timing of a second edge of the first clock signal;
• generating a fourth clock signal and a fifth clock signal by phase interpolation of the second clock signal, the third clock signal, an first inverted signal that is obtained by inverting the second clock signal, or an second inverted signal that is obtained by inverting the third clock signal;
• and
• outputting an exclusive OR signal of the fourth clock signal and the fifth clock signal as a sixth clock signal.