Low power oversampling with reduced-architecture delay locked loop

A system, comprising:

• a system on a chip comprising at least one core having at least one execution unit and receiver logic, the receiver logic comprising:
• a digital delay-locked loop circuit to:
• receive a reference pulse-width modulated (PWM) clock signal and a gear selection input;
• invert the reference PWM clock signal;
• determine a phase difference between the inverted reference PWM clock signal and a feedback clock signal;
• generate a plurality of phase output signals based on the phase difference;
• and
• a clock generator device to generate an oversampled clock signal based on the plurality of phase output signals, the oversampled clock signal to be used for data recovery by the receiver logic;
• and
• a wireless device coupled to the system on the chip via an interconnect, the interconnect used to communicate data between the wireless device and the receiver logic of the system on the chip.

A method, comprising:

• determining, in an oversampling logic unit of a receiver, a phase difference between an inverted reference clock signal and a feedback clock signal;
• generating a delay signal based on the phase difference;
• receiving a gear selection input that identifies one of a plurality of speed ranges according to a low power communication specification;
• generating a plurality of phase outputs using a delay-locked loop circuit of the oversampling logic unit;
• and
• generating an oversampled clock signal based on the plurality of phase outputs, the oversampled clock signal for use in performing data recovery by the receiver.