Semiconductor device having DLL circuit and control method thereof
AssigneePS4 Luxco S.a.r.l.
InventorHideyuki Ichida
Life of this patent
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Abstract
Disclosed herein is a device that comprises a delay line delaying a first clock signal in response to the delay control information to produce a delayed clock signal, a phase detector unit controls the delay control information in response to a relationship in phase between the first clock signal and a second clock signal, and an inverting control unit receiving the delayed clock signal and producing a third clock signal, the second clock signal being produced in response to the third clock signal. The third clock signal is in phase with the delayed clock signal when the inverting control unit is in a first state and complementary to the delayed clock signal when the inverting control unit is in a second state.
Claims16
A device comprising:
- a delay line unit supplied with delay control information, the delay line configured to delay a first clock signal in response to the delay control information to produce a delayed clock signal;
- a phase detector unit supplied with the first clock signal and a second clock signal and configured to control the delay control information in response to a relationship in phase between the first and second clock signals;
- and
- a circuit unit coupled between the delay line unit and the phase detector unit, the circuit unit including an inverting control unit configured to receive the delayed clock signal and to produce a third clock signal, the third clock signal being in phase with the delayed clock signal when the inverting control unit is in a first state and complementary to the delayed clock signal when the inverting control unit is in a second state, the circuit unit being configured to produce the second clock signal as a replica signal in response to the third clock signal.
A device comprising:
- a counter unit configured to generate a count value;
- a delay line configured to delay a first clock signal based on the count value to generate a second clock signal;
- an inversion control unit configured to select one of a non-inverted signal of the second clock signal and an inverted signal of the second clock signal to output a third clock signal;
- a replica output unit configured to generate a fourth clock signal based on the third clock signal;
- a phase comparison unit configured to compare phases of the first and fourth clock signals to generate a phase determination signal;
- and
- a control unit configured to generate a reset signal, an inversion control signal, a code update signal, and a counter update signal, wherein
- the count value of the counter unit is initialized to a first initial value and the inversion control unit selects the non-inverted signal when the reset signal is activated,
- the inversion control unit is configured to select one of the non-inverted signal and the inverted signal based on a logic level of the phase determination signal when the inversion control signal is activated,
- the count value of the counter unit is updated from the first initial value to a second initial value when the code update signal is activated after the inversion control signal is activated, and
- the count value of the counter unit is counted up or counted down from the second initial value based on a logic level of the phase determination signal when the counter update signal is activated.
A method comprising:
- delaying a first clock signal to produce a delayed clock signal;
- producing an inverted signal of the delayed clock signal;
- detecting a relationship in phase between the first clock signal and a second clock signal to produce a detection signal;
- selecting one of the delayed signal and the inverted signal in response to the detection signal;
- and
- producing the second clock signal as a replica signal in response to a selected one of the delayed signal and the inverted signal.
Dependencies are inferred from the claim text.