Pulse generation circuits in integrated circuits

A pulse generation circuit comprising:

• one or more delay blocks positioned in a serial configuration so as to be positioned to generate a power on reset (POR) pulse, each delay block comprising:
• an inverter comprising an output terminal and configured by a NMOS transistor and a PMOS transistor, the inverter configured to receive an input signal and provide an inverted input signal at the output terminal;
• a Metal Oxide Semiconductor (MOS) based resistor comprising a first node and a second node, the first node coupled with the output terminal so as to be positioned to receive the inverted input signal and provide the inverted input signal to the second node;
• an amplifier circuit comprising an inverting voltage amplifier, which comprises an input node and an output node, and a miller capacitor coupled between the input node and the output node, a charging and discharging of an equivalent capacitor at the input node being configured to generate a pulse of a pre-determined width at the output node;
• and
• a Schmitt trigger buffer coupled with the output node and comprising an output node, the Schmitt trigger configured to receive the pulse of pre-determined width and provide a portion of the POR pulse at the output node, the input signal received by the inverter being a sense signal for a first delay block in the serial configuration, the input signal being an output of a Schmitt trigger buffer of a preceding delay block in the serial configuration for each of the remaining delay blocks in the serial configuration, and the one or more delay blocks being configured to generate the POR pulse of a threshold duration;
• wherein the each delay block further comprises:
• a MOS based circuit coupled with an input node of the Schmitt trigger buffer, the MOS based circuit configuring to provide a signal to the input of the Schmitt trigger buffer to provide a pre-determined state at the output node of the Schmitt trigger buffer, in response to the input signal that is received at the inverter;
• and
• a loading circuit coupled with the first node of the MOS based resistor for increasing load at the first node of the MOS based resistor, wherein the MOS based resistor is configured in a diode based configuration.