Power-on reset circuit
AssigneeSeiko Instruments Inc.
InventorTomohiro Oka
Life of this patent
Estimating the term…
Abstract
The power-on reset circuit includes: a NMOS transistor having a source connected to a second power supply terminal and a gate connected to a drain thereof; a depletion-type NMOS transistor having a source connected to the drain of the NMOS transistor, a drain connected to a first power supply terminal and a gate connected to the second power supply terminal; a PMOS transistor having a source connected to the first power supply terminal, a gate connected to the drain of the NMOS transistor and a drain; a capacitor having one end connected to the drain of the PMOS transistor and the other end connected to the second power supply terminal; and a waveform shaping circuit having an input terminal connected to the drain of the PMOS transistor and an output terminal from which a power-on reset signal is output.
Claims1
A power-on reset circuit, comprising:
- a NMOS transistor having a source connected to a second power supply terminal and a gate connected to a drain thereof;
- a depletion-type NMOS transistor having a source connected to the drain of the NMOS transistor, a drain connected to a first power supply terminal and a gate connected to the second power supply terminal;
- a PMOS transistor having a source connected to the first power supply terminal, a gate connected to the drain of the NMOS transistor and a drain;
- a capacitor having one end connected to the drain of the PMOS transistor and the other end connected to the second power supply terminal;
- and
- a waveform shaping circuit having an input terminal connected to the drain of the PMOS transistor and an output terminal from which a power-on reset signal is output.
Dependencies are inferred from the claim text.