High speed RF divider

A Radio Frequency (RF) quadrature clock divider comprising:

• positive and negative differential RF clock inputs;
• first positive and negative differential RF clock outputs having half the frequency of the clock inputs;
• second positive and negative differential RF clock outputs having half the frequency of the clock inputs and a 90-degree phase offset from the first RF clock outputs;
• a first plurality of transistors configured as first inverters, wherein each of the first inverters comprises a PMOS transistor serially connected to an NMOS transistor;
• a second plurality of transistors configured as clocking circuits, each clocking circuit associated with a first inverter, wherein each clocking circuit comprises a PMOS transistor interposed between an inverter and a positive voltage supply node and an NMOS transistor interposed between the inverter and a ground node;
• wherein each associated first inverter and clocking circuit comprises a stage, and a plurality of such stages are connected in a serial ring formation;
• and
• a second inverter interposed between each stage;
• wherein the positive clock input is connected to one transistor in each clocking circuit and the negative clock input is connected to one transistor in each clocking circuit, such that the positive and negative clock inputs alternate at each successive clocking circuit in the ring.