Detection of bad clock conditions
AssigneeSTMicroelectronics (Research & Development) Limited
InventorMark Trimmer
Life of this patent
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Abstract
There is provided a circuit and method for detecting a bad clock condition on a clock signal that includes sampling the value of the clock signal at a first plurality of time delays following a rising edge on the clock signal. This method also includes sampling the value of the clock signal at a second plurality of time delays following a falling edge on the clock signal.
Claims20
A method of detecting a bad clock condition on a clock signal, the method comprising:
- sampling a value of the clock signal at each of a first plurality of time delays timed following an edge of the clock signal to encompass a successive edge of the clock signal;
- determining whether all of the first plurality of samples have a same logic state;
- and
- signaling that the bad clock condition exists if all of the first plurality of samples have the same logic state.
A circuit for detecting a bad clock condition on a clock signal, the circuit comprising:
- a first sampling unit configured to sample a value of the clock signal at each of a first plurality of time delays following an edge on the clock signal to encompass a successive edge of the clock signal;
- a first determining unit configured to determine whether all of the first plurality of samples have a same logic state;
- and
- a clock condition determining unit configured to determine that the bad clock condition exists on the clock signal if all of the first plurality of samples are determined to have the same logic state.
A computer system for processing data using a clock signal, comprising:
- a circuit configured to detect a bad clock condition on the clock signal, the circuit comprising:
- a sampling unit configured to sample a value of the clock signal at each of a plurality of time delays following an edge on the clock signal to encompass a successive edge of the clock signal;
- a determining unit configured to determine whether all of the plurality of samples have a same logic state;
- and
- a clock condition determining unit configured to determine that the bad clock condition exists on the clock signal if all of the plurality of samples are determined to have the same logic state.
Dependencies are inferred from the claim text.