Hybrid H-bridge and CML driver
AssigneeLattice Semiconductor Corporation
InventorsVinh Ho, Magathi Jayaram, Allan Lin
Life of this patent
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Abstract
In one embodiment, a hybrid output buffer having both an H-bridge mode and a CML mode of operation includes a plurality of transistor switches arranged between an upper rail and a bottom rail. A first pair of the transistor switches couples between the upper rail and respective output nodes. A pair of resistors couples between the output nodes and a central node. During H-bridge mode, the hybrid output buffer controls a potential of the upper rail responsive to a feedback signal proportional to a difference between a potential of the central node and a common-mode voltage.
Claims20
A hybrid circuit comprising:
- a pair of resistors coupled through a central node;
- a mode control circuit configured to charge the central node to a supply voltage in a current mode logic (CML) mode of operation and to allow the central node to float in an H-bridge mode of operation;
- a differential amplifier configured to compare a potential of the central node to a common-mode voltage to provide a feedback signal;
- and
- a first PMOS transistor having its gate driven by the feedback signal, the first PMOS transistor having it source coupled to the supply voltage and a drain coupled to an upper rail for the hybrid circuit.
A method, comprising:
- in a hybrid output buffer, receiving a mode signal having a first state and a second state;
- responsive to receiving the current mode signal in the first state, charging a central node of the hybrid output buffer to a power supply potential and operating the hybrid output buffer in a current mode logic (CML) mode;
- responsive to receiving the current mode signal in the second state, floating a potential of central node and operating the hybrid output buffer in an H-bridge mode;
- and
- while operating in the H-bridge mode, controlling a potential of an upper rail for the hybrid output buffer in response to a feedback signal that is proportional to a difference between the potential of the central node and a common-mode voltage.
A circuit, comprising:
- a first resistor;
- a second resistor coupled to the first resistor through a central node;
- a plurality of hybrid output buffers that share the first and second resistors and the central node;
- and
- a mode control circuit configured to charge the central node to a supply voltage in a current mode logic (CML) mode of operation and to allow the central node to float in an H-bridge mode of operation.
Dependencies are inferred from the claim text.