US 8,797,061 B2 · Partial reconfiguration circuitry

Abstract

Integrated circuits may include partial reconfiguration (PR) circuitry for reconfiguring a portion of a memory array. The PR circuitry may include a host circuit, a control circuit, an address register, and first, second, and third data registers. The host circuit may send a series of PR instructions to the control circuit. The control circuit may include a decompression circuit for decompressing compressed instructions, a decryption circuit for decrypting encrypted instructions, an error checking circuit for detecting errors in the instructions, and a logic circuit. The address register may select a desired frame. The selected frame may be loaded into the third data register. The contents of the third data register may be shifted into the first data register. The contents of the first data register may be modified according to a desired logic function using the logic circuit, shifted into the second data register, and written into the selected frame.

Claims19

Dependent claims

An integrated circuit comprising:

an array of memory elements;
and
partial reconfiguration circuitry that is coupled to the array of memory elements, wherein the partial reconfiguration circuitry comprises:
a control circuit;
and
data register circuitry that stores data that is read from a selected row of memory elements in the array of memory elements and to modify the read data to produce modified data, wherein the control circuit loads the modified data from the data register circuitry into the selected row of memory elements in the array of memory elements, wherein the control circuit includes a configurable logic circuit that produces the modified data by using the configurable logic circuit to implement a logic function selected from the group consisting of:
a logic AND function, a logic OR function, a logic XOR function, a logic NAND function, a logic NOR function, and a logic XNOR function.

4 more elements

An integrated circuit comprising:

an array of memory elements;
and
partial reconfiguration circuitry that is coupled to the array of memory elements, wherein the partial reconfiguration circuitry comprises:
a control circuit;
and
data register circuitry that stores data that is read from a selected row of memory elements in the array of memory elements and to modify the read data to produce modified data, wherein the control circuit loads the modified data from the data register circuitry into the selected row of memory elements in the array of memory elements, wherein the control circuit also receives a plurality of partial reconfiguration instructions, and wherein the control circuit includes a configurable logic circuit that produces the modified data based on a given partial reconfiguration instruction in the plurality of partial reconfiguration instructions.

3 more elements

A method of operating partial reconfiguration circuitry that is coupled to an array of memory elements, wherein the partial reconfiguration circuitry and the array of memory elements are formed on an integrated circuit, and wherein the partial reconfiguration circuitry includes a control circuit, an address register, and data register circuitry, the method comprising:

with the control circuit, receiving a plurality of partial reconfiguration instructions, wherein a given partial reconfiguration instruction in the plurality of partial reconfiguration instructions includes partial reconfiguration memory data;
reading data from a selected row of memory elements in the array of memory elements and loading the read data into a first data register in the data register circuitry;
loading the read data from the first data register to a second data register in the data register circuitry;
modifying the read data that is stored in the data register circuitry based at least partially on the read data and the partial reconfiguration memory data, wherein the control circuit includes a configurable logic circuit and wherein modifying the read data that is stored in the data register circuitry comprises generating the modified data with the configurable logic circuit and serially shifting the modified data that is generated by the logic circuit into the second data register;
and
loading the modified data into the selected row of memory elements.

3 more elements

Dependencies are inferred from the claim text.

Partial reconfiguration circuitry

Life of this patent

Partial reconfiguration circuitry

Life of this patent

Abstract

Claims19