Thermal and stress gradient based RC extraction, timing and power analysis
AssigneeQUALCOMM Incorporated
InventorsHongmei Liao, Riko Radojcic
Life of this patent
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Abstract
Timing, power and SPICE analysis are performed on a circuit layout, based on temperature and stress variations or gradient across the circuit layout. Specifically, the temperature and stress values of individual window locations across the layout are used to obtain temperature and stress variation aware resistance/capacitance (RC), timing, leakage and power values. In addition, in 3D integrated circuits (IC), the stress and thermal variations or gradients of one die may be imported to another die located on a different tier.
Claims26
A method of circuit layout analysis, comprising:
- analyzing a range of temperature values and a range of stress values for each of a plurality of regions across a circuit layout;
- and
- calculating region specific resistance capacitance (RC) parasitic values for each region in the plurality of regions across the circuit layout based on the analyzed temperature and stress values of a corresponding region in the plurality of regions across the circuit layout.
An apparatus for circuit layout analysis, comprising:
- means for analyzing a range of temperature values and a range of stress values for each of a plurality of regions across a circuit layout;
- and
- means for calculating region specific resistance capacitance (RC) parasitic values for each region in the plurality of regions across the circuit layout based on the analyzed temperature and stress values of a corresponding region in the plurality of regions across the circuit layout.
A computer readable medium storing non-transitory program code for circuit layout analysis, comprising:
- program code to analyze a range of temperature values and a range of stress values for each of a plurality of regions across a circuit layout;
- and
- program code to calculate region specific resistance capacitance (RC) parasitic values for each region in the plurality of regions across the circuit layout based on the analyzed temperature and stress values of a corresponding region in the plurality of regions across the circuit layout.
A method of circuit layout analysis, comprising:
- the step for analyzing a range of temperature values and a range of stress values for each of a plurality of regions across a circuit layout;
- and
- the step for calculating window location specific resistance capacitance (RC) parasitic values for each region in the plurality of regions across the circuit layout based on the analyzed temperature and stress values of a corresponding region in the plurality of regions across the circuit layout.
An apparatus for circuit layout analysis, comprising:
- a memory;
- and
- at least one processor coupled to the memory and configured:
- to analyze a range of temperature values and a range of stress values for each of a plurality of regions across a circuit layout;
- and
- to calculate region specific resistance capacitance (RC) parasitic values for each region in the plurality of regions across the circuit layout based on the analyzed temperature and stress values of a corresponding region in the plurality of regions across the circuit layout.
Dependencies are inferred from the claim text.