Semiconductor memory devices and semiconductor packages
AssigneeSamsung Electronics Co., Ltd.
InventorsHo-Cheol Lee, Chi-Sung Oh, Jin-Kuk Kim
Life of this patent
Estimating the term…
Abstract
A semiconductor memory device includes a semiconductor die and an input-output bump pad part. The semiconductor die includes a plurality of memory cell arrays. The input-output bump pad part is formed in a central region of the semiconductor die. The input-output bump pad part provides a plurality of channels for connecting each of the memory cell arrays independently to an external device. The semiconductor memory device may adopt the multi-channel interface, thereby having high performance with relatively low power consumption.
Claims24
A semiconductor memory device comprising:
- a semiconductor die including
- a plurality of memory cell arrays;
- and
- an input-output bump pad part located at a central region of the semiconductor die, the input-output bump pad part providing a plurality of channels each dedicated to only a respective one of the memory cell arrays and by which each of the memory cell arrays can be connected independently of each other to one or more external devices, and
- wherein the input-output bump pad part includes a plurality of channel bump pad parts associated with the memory cell arrays, respectively,
- each of the channel bump pad parts includes a plurality of bump pads that are arranged in a matrix of rows and columns, and
- the bump pads of each of the channel bump parts include power bump pads dedicated to receive power supply voltages.
A semiconductor memory device, comprising:
- a semiconductor die including
- a plurality of memory cell arrays,
- an input-output bump pad part located at a central region of the semiconductor die, the input-output bump pad part providing a plurality of channels each dedicated to only a respective one of the memory cell arrays and by which each of the memory cell arrays can be connected independently of each other to one or more external devices, and
- a test pad part for testing operations of the semiconductor memory device.
A semiconductor memory device, comprising:
- a semiconductor die including
- a plurality of memory cell arrays,
- an input-output bump pad part located at a central region of the semiconductor die, the input-output bump pad part providing a plurality of channels each dedicated to only a respective one of the memory cell arrays and by which each of the memory cell arrays can be connected independently of each other to one or more external devices, and
- a support bump pad part disposed adjacent to four corners of the semiconductor die or disposed adjacent to two or more sides of the semiconductor die.
Dependencies are inferred from the claim text.