Three dimensional memory structure
OwnerGlenn J Leedyinventor
Life of this patent
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Abstract
A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 microns in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.
Claims162
A stacked circuit structure comprising:
- a plurality of stacked, thin, substantially flexible circuit layers each comprising a top surface and a bottom surface and at least one of which comprises a thinned, substantially flexible monocrystalline semiconductor substrate of one piece;
- and
- an interlayer region disposed between a pair of vertically adjacent circuit layers and extending from a top surface of one of the pair of vertically adjacent circuit layers to a bottom surface of another one of the pair of vertically adjacent circuit layers, the interlayer region comprising an interlayer for providing mechanical attachment and electrical interconnection between the pair of vertically adjacent circuit layers;
- wherein within the interlayer region the stacked circuit structure consists essentially of metal or metal and silicon-based dielectric.
A stacked circuit structure comprising:
- a plurality of stacked, thin, substantially flexible circuit layers at least one of which comprises a thinned, substantially flexible monocrystalline semiconductor substrate of one piece;
- wherein a pair of vertically adjacent circuit layers is joined together using metal-to-metal bonding as a mechanism of both attachment and electrical interconnection.
A stacked circuit structure comprising:
- a plurality of stacked, thin, substantially flexible circuit layers at least one of which comprises a thinned, substantially flexible monocrystalline semiconductor substrate of one piece;
- wherein a pair of adjacent stacked, thin, substantially flexible circuit layers is bonded together at least with metal, or at least with silicon-based dielectric and metal.
A stacked circuit structure comprising:
- a plurality of stacked, thin, substantially flexible circuit layers at least one of which comprises a thinned, substantially flexible monocrystalline semiconductor substrate of one piece;
- wherein at least one of the substantially flexible circuit layers comprises at least one memory array comprising memory cells and a low stress silicon-based dielectric material;
- and
- at least one vertical interconnection that passes through at least one of the plurality of stacked, thin, substantially flexible circuit layers.
The stacked circuit structure of 105, wherein at least one block stack of the plurality of block stacks comprises at least one memory array controller block further comprising reconfiguration circuitry that performs reconfiguration of the array of vertical interconnects to avoid using one or more defective vertical interconnects of the at least one block stack.
A stacked integrated circuit structure comprising:
- at least one thin, substantially flexible integrated circuit layer comprising at least a thinned, substantially flexible monocrystalline semiconductor substrate of one piece having a backside;
- at least one low-stress silicon-based dielectric layer formed above the thinned, substantially flexible monocrystalline semiconductor substrate, wherein the low-stress silicon-based dielectric layer has a stress of less than 5×108 dynes/cm2 tensile;
- and
- a plurality of memory circuit layers each memory circuit layer comprising at least one silicon-based low stress dielectric layer and at least one conductive layer, wherein the at least one low-stress silicon-based dielectric layer has a stress of less than 5×108 dynes/cm2 tensile.
A substantially flexible stacked integrated circuit structure comprising:
- at least one thin, substantially flexible integrated circuit layer comprising a thinned, substantially flexible monocrystalline semiconductor substrate of one piece having a backside, wherein the backside of the thinned, substantially flexible monocrystalline semiconductor substrate is polished or smoothed, wherein the polished or smoothed backside enables the thinned, monocrystalline semiconductor substrate to be substantially flexible, and the polished or smoothed backside reduces the vulnerability of the thinned, substantially flexible monocrystalline semiconductor substrate to fracture as a result of flexing;
- at least one low-stress silicon-based dielectric layer formed above the thinned, substantially flexible monocrystalline semiconductor substrate, wherein the at least one low-stress silicon-based dielectric layer has a stress of less than 5×108 dynes/cm2 tensile;
- and
- a plurality of memory circuit layers, wherein each memory circuit layer comprises at least one silicon-based low stress dielectric layer and at least one conductive layer, wherein the at least one low-stress silicon-based dielectric layer has a stress of less than 5×108 dynes/cm2 tensile;
- wherein the substantially flexible stacked integrated circuit structure is substantially flexible through combination of the thinned, substantially flexible monocrystalline semiconductor substrate having a polished or smoothed backside, low stress of the at least one low stress silicon-based dielectric layer, and low stress of the at least one silicon-based low stress dielectric layer of the plurality of memory circuit layers.
Dependencies are inferred from the claim text.