3D integrated circuit structure and method for manufacturing the same

A method for manufacturing a 3D integrated circuit structure, comprising:

• A. providing a first chip, wherein the first chip comprises a first substrate, a first semiconductor device and a first dielectric layer, and wherein the first semiconductor device is formed on the first substrate, and the first dielectric layer is formed on both the first substrate and the first semiconductor device;
• B. forming a through hole, a stress passage isolation layer and a stress releasing layer which penetrate both the first substrate and the first dielectric layer, wherein the stress passage isolation layer surrounds the outside of the through hole and the stress releasing layer surrounds the outside of the stress passage isolation layer;
• B′. forming an insulating layer on inside walls of the stress passage isolation layer;
• C. filling the through hole to form a conductive material layer;
• and
• D. forming a first interconnecting structure for connecting the first semiconductor device with the conductive material layer,
• wherein the step B comprises:
• forming a photoresist pattern according to the patterns of the through hole and the stress releasing layer which are to be formed;
• and
• etching the first substrate and the first dielectric layer according to the photoresist pattern to form the through hole and a stress releasing passage,
• wherein the stress releasing layer is formed from the stress releasing passage, and the stress passage isolating layer is formed between the through hole and the stress releasing layer,
• wherein the step D comprises:
• forming an external stop layer on internal sidewalls of the through hole;
• and
• forming an internal conductive via in the external stop layer.